ジャーナル論文 Van der Waals polarity-engineered 3D integration of 2D complementary logic
Yimeng Guo (author) (この著者で検索)
;
Jiangxu Li (author) (この著者で検索)
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Xuepeng Zhan (author) (この著者で検索)
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Chunwen Wang (author) (この著者で検索)
;
Min Li (author) (この著者で検索)
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Biao Zhang (author) (この著者で検索)
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Zirui Wang (author) (この著者で検索)
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Yueyang Liu (author) (この著者で検索)
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Kaining Yang (author) (この著者で検索)
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Hai Wang (author) (この著者で検索)
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Wanying Li (author) (この著者で検索)
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Pingfan Gu (author) (この著者で検索)
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Zhaoping Luo (author) (この著者で検索)
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Yingjia Liu (author) (この著者で検索)
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Peitao Liu (author) (この著者で検索)
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Bo Chen (author) (この著者で検索)
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Kenji Watanabe (author) (この著者で検索)
ORCID SAMURAI ;
Takashi Taniguchi (author) (この著者で検索)
ORCID SAMURAI ;
Xing-Qiu Chen (author) (この著者で検索)
;
Chengbing Qin (author) (この著者で検索)
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Jiezhi Chen (author) (この著者で検索)
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Dongming Sun (author) (この著者で検索)
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Jing Zhang (author) (この著者で検索)
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Runsheng Wang (author) (この著者で検索)
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Jianpeng Liu (author) (この著者で検索)
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Yu Ye (author) (この著者で検索)
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Xiuyan Li (author) (この著者で検索)
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Yanglong Hou (author) (この著者で検索)
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Wu Zhou (author) (この著者で検索)
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Hanwen Wang (author) (この著者で検索)
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Zheng Han (author) (この著者で検索)
コレクション

引用
Yimeng Guo, Jiangxu Li, Xuepeng Zhan, Chunwen Wang, Min Li, Biao Zhang, Zirui Wang, Yueyang Liu, Kaining Yang, Hai Wang, Wanying Li, Pingfan Gu, Zhaoping Luo, Yingjia Liu, Peitao Liu, Bo Chen, Kenji Watanabe, Takashi Taniguchi, Xing-Qiu Chen, Chengbing Qin, Jiezhi Chen, Dongming Sun, Jing Zhang, Runsheng Wang, Jianpeng Liu, Yu Ye, Xiuyan Li, Yanglong Hou, Wu Zhou, Hanwen Wang, Zheng Han. Van der Waals polarity-engineered 3D integration of 2D complementary logic. Nature. 2024, 630 (8016), 346-352. https://doi.org/10.1038/s41586-024-07438-5

説明:

(abstract)

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1,2,3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6,7,8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9,10,11,12,13,14,15,16,17) and MoS2 (refs. 11,18,19,20,21,22,23,24,25,26,27,28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V−1 s−1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

権利情報:

キーワード: Polarity Engineering of 2D Semiconductors, Vertically Integrated Logic Circuits, van der Waals Interfacial Coupling

刊行年月日: 2024-06-13

出版者: Springer Science and Business Media LLC

掲載誌:

  • Nature (ISSN: 00280836) vol. 630 issue. 8016 p. 346-352

研究助成金:

原稿種別: 出版者版 (Version of record)

MDR DOI:

公開URL: https://doi.org/10.1038/s41586-024-07438-5

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更新時刻: 2025-08-02 08:30:31 +0900

MDRでの公開時刻: 2025-08-02 08:17:30 +0900

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