All-2D ReS2 transistors with split gates for logic circuitry

Article

Creator

Junyoung Kwon ; Yongjun Shin ; Hyeokjae Kwon ; Jae Yoon Lee ; Hyunik Park ; Kenji Watanabe ; Takashi Taniguchi ; Jihyun Kim ; Chul-Ho Lee ; Seongil Im ; Gwan-Hyoung Lee

Keyword

2D semiconductors, van der Waals heterostructure, NAND gate

Date published

2019-07-17

Updated at

2025-02-23 22:50:28 +0900