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Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design
- Journal article
- Creator
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;Mu-Pai Lee (author) (Search by this author);Caifang Gao (author) (Search by this author);Meng-Yu Tsai (author) (Search by this author);Che-Yi Lin (author) (Search by this author);Feng-Shou Yang (author) (Search by this author);Hsin-Ya Sung (author) (Search by this author);Chi Zhang (author) (Search by this author);Wenwu Li (author) (Search by this author);Jun Li (author) (Search by this author);Jianhua Zhang (author) (Search by this author)Kenji Watanabe (author) (Search by this author)National Institute for Materials Science
;
Takashi Taniguchi (author) (Search by this author)National Institute for Materials Science
;
;Keiji Ueno (author) (Search by this author)Kazuhito Tsukagoshi (author) (Search by this author)National Institute for Materials Science
;
;Ching-Hwa Ho (author) (Search by this author);Junhao Chu (author) (Search by this author);Po-Wen Chiu (author) (Search by this author);Mengjiao Li (author) (Search by this author);Wen-Wei Wu (author) (Search by this author)Yen-Fu Lin (author) (Search by this author) - Keyword
- van der Waals, 2D/3D heterointegration
- Date published
- 2023-12-08
- Updated at
- 2025-02-10 16:30:24 +0900