Article Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design

Mu-Pai Lee ; Caifang Gao ; Meng-Yu Tsai ; Che-Yi Lin ; Feng-Shou Yang ; Hsin-Ya Sung ; Chi Zhang ; Wenwu Li ; Jun Li ; Jianhua Zhang ; Kenji Watanabe SAMURAI ORCID (National Institute for Materials ScienceROR) ; Takashi Taniguchi SAMURAI ORCID (National Institute for Materials ScienceROR) ; Keiji Ueno ; Kazuhito Tsukagoshi SAMURAI ORCID (National Institute for Materials ScienceROR) ; Ching-Hwa Ho ; Junhao Chu ; Po-Wen Chiu ; Mengjiao Li ; Wen-Wei Wu ; Yen-Fu Lin

Lee et al., 2023, Silicon – van der Waals heterointegration for CMOS- compatible logic-in-memory design.pdf
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Mu-Pai Lee, Caifang Gao, Meng-Yu Tsai, Che-Yi Lin, Feng-Shou Yang, Hsin-Ya Sung, Chi Zhang, Wenwu Li, Jun Li, Jianhua Zhang, Kenji Watanabe, Takashi Taniguchi, Keiji Ueno, Kazuhito Tsukagoshi, Ching-Hwa Ho, Junhao Chu, Po-Wen Chiu, Mengjiao Li, Wen-Wei Wu, Yen-Fu Lin. Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design. Science Advances. 2023, 49 (9), adk1597.
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(abstract)

The intensive data-centered computational requirement leads to the development of a computing-in-memory architecture that can blur the boundary between memory and process units. However, the implementation of silicon CMOS-based computing-in- memory faces challenges in complicated circuit design and static power dissipation, especially in a digital manner, i.e., logic-in-memory, which requires both nonvolatility and reconfigurability. Here, we report a universal design of nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By exploiting the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Two critical merits jointly enable desirable performance, including precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85 °C), and near-ideal subthreshold swing (80 mV dec1 ). A comprehensive investigation of dynamic charge fluctuations offers a holistic understanding of the nonvolatile reconfigurability origins (a trap level of 10E13 cm2 eV1 ). We further cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as a high-gain (65 at V dd = 0.5 V) logic inverter and logic gates. Our devices with simplified circuit design and manufacturing provide an innovative 3D heterointegration prototype for future computing-in-memory hardware.

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Keyword: van der Waals, 2D/3D heterointegration

Date published: 2023-12-08

Publisher: American Association for the Advancement of Science (AAAS)

Journal:

  • Science Advances (ISSN: 23752548) vol. 49 issue. 9 adk1597

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Manuscript type: Publisher's version (Version of record)

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First published URL: https://doi.org/10.1126/sciadv.adk1597

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Updated at: 2025-02-10 16:30:24 +0900

Published on MDR: 2025-02-10 16:30:24 +0900

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