Download file (1.24MB)
Download as zip (1.04MB)

コレクション

引用

説明:

The intensive data-centered computational requirement leads to the development of a computing-in-memory architecture that can blur the boundary between memory and process units. However, the implementation of silicon CMOS-based computing-in- memory faces challenges in complicated circuit design and static power dissipation, especially in a digital manner, i.e., logic-in-memory, which requires both nonvolatility and reconfigurability. Here, we report a universal design of nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By exploiting the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Two critical merits jointly enable desirable performance, including precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85 °C), and near-ideal subthreshold swing (80 mV dec1 ). A comprehensive investigation of dynamic charge fluctuations offers a holistic understanding of the nonvolatile reconfigurability origins (a trap level of 10E13 cm2 eV1 ). We further cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as a high-gain (65 at V dd = 0.5 V) logic inverter and logic gates. Our devices with simplified circuit design and manufacturing provide an innovative 3D heterointegration prototype for future computing-in-memory hardware.

権利情報:

• Creative Commons BY Attribution 4.0 International
  

キーワード: van der Waals, 2D/3D heterointegration

刊行年月日: 2023-12-08

出版者: American Association for the Advancement of Science (AAAS)

掲載誌:

• Science Advances (ISSN: 23752548) vol. 49 issue. 9 adk1597

研究助成金:

原稿種別: 出版者版 (Version of record)

MDR DOI:

公開URL: https://doi.org/10.1126/sciadv.adk1597

関連資料:

その他の識別子:

連絡先:

更新時刻: 2025-02-10 16:30:24 +0900

MDRでの公開時刻: 2025-02-10 16:30:24 +0900