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説明:

Ferroelectricity, one of the keys to realize non-volatile memories owing to the remanent electric polarization, is an emerging phenomenon in the 2D limit. Yet the demonstrations of van der Waals (vdW) memories using 2D ferroelectric materials as an ingredient are very limited. Especially, gate-tunable ferroelectric vdW memristive device, which holds promises in future multi-bit data storage applications, remains challenging. Here, a gate-programmable multi-state memory is shown by vertically assembling graphite, CuInP2S6, and MoS2 layers into a metal(M)-ferroelectric(FE)-semiconductor(S) architecture. The resulted devices seamlessly integrate the functionality of both FE-memristor (with ONーOFF ratios exceeding 105 and long-term retention) and metal-oxide-semiconductor field effect transistor (MOS-FET). Thus, it yields a prototype of gate tunable giant electroresistance with multi-levelled ON-states in the FE-memristor in the vertical vdW assembly. First-principles calculations further reveal that such behaviors originate from the specific band alignment between the FE-S interface. Our findings pave the way for the engineering of ferroelectricity-mediated memories in future implementations of 2D nanoelectronics.

権利情報:

• Creative Commons BY Attribution 4.0 International
  

キーワード: Ferroelectricity, van der Waals memories, gate-tunable

刊行年月日: 2022-12-18

出版者: Wiley

掲載誌:

• Advanced Materials (ISSN: 15214095) vol. 35 issue. 5 2208266

研究助成金:

• National Natural Science Foundation of China 11974357
• National Natural Science Foundation of China 12104462
• National Natural Science Foundation of China 92265203
• National Natural Science Foundation of China U1932151

原稿種別: 出版者版 (Version of record)

MDR DOI:

公開URL: https://doi.org/10.1002/adma.202208266

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更新時刻: 2025-02-14 12:31:45 +0900

MDRでの公開時刻: 2025-02-14 12:31:45 +0900