Gating monolayer and bilayer graphene with a two-dimensional semiconductor

Randy M. Sterbentz; Bogyeom Kim; Anayeli Flores-Garibay; Kristine L. Haley; Nicholas T. Pereira; Kenji Watanabe; Takashi Taniguchi; Joshua O. Island

doi:10.1038/s41699-025-00551-7

論文 Gating monolayer and bilayer graphene with a two-dimensional semiconductor

Randy M. Sterbentz ; Bogyeom Kim ; Anayeli Flores-Garibay ; Kristine L. Haley ; Nicholas T. Pereira ; Kenji Watanabe (National Institute for Materials Science) ; Takashi Taniguchi (National Institute for Materials Science) ; Joshua O. Island

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Randy M. Sterbentz, Bogyeom Kim, Anayeli Flores-Garibay, Kristine L. Haley, Nicholas T. Pereira, Kenji Watanabe, Takashi Taniguchi, Joshua O. Island. Gating monolayer and bilayer graphene with a two-dimensional semiconductor. npj 2D Materials and Applications. 2025, 9 (1), 29. https://doi.org/10.1038/s41699-025-00551-7

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(abstract)

Metals are typically used as electrostatic gates in devices due to their abundant charge carrier densities that are necessary for efficient charging and discharging. A semiconducting gate can be beneficial for certain fabrication processes, in low light conditions, and for specific gating properties. Here, we determine the effectiveness and limitations of a semiconducting gate in graphene and bilayer graphene devices. Using the semiconducting transition metal dichalcogenides molybdenum disulfide (MoS2) and molybdenum diselenide (MoSe2), we show that these semiconductors can be used to suitably gate the graphene devices for certain operating conditions. For singly gated devices, we find that the semiconducting gates provide gating characteristics comparable with metallic gates below liquid helium temperatures but include resistivity features resulting from gate voltage clamping of the MoS2. A 1D potential model is developed that corroborates the clamping effect observed in the measurements. In doubly gated devices, we pin down the parameter range of effective operation and show that the semiconducting depletion regime results in clamping and hysteresis from defect state charge trapping. Our results provide a guide for the appropriate operating conditions for employing semiconducting gates and open the door to novel device architectures.

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