Journal article All-2D ReS2 transistors with split gates for logic circuitry
Junyoung Kwon (author) (Search by this author)
;
Yongjun Shin (author) (Search by this author)
;
Hyeokjae Kwon (author) (Search by this author)
;
Jae Yoon Lee (author) (Search by this author)
;
Hyunik Park (author) (Search by this author)
;
Kenji Watanabe (author) (Search by this author)
ORCID SAMURAI ;
Takashi Taniguchi (author) (Search by this author)
ORCID SAMURAI ;
Jihyun Kim (author) (Search by this author)
;
Chul-Ho Lee (author) (Search by this author)
;
Seongil Im (author) (Search by this author)
;
Gwan-Hyoung Lee (author) (Search by this author)
Collection

Citation
Junyoung Kwon, Yongjun Shin, Hyeokjae Kwon, Jae Yoon Lee, Hyunik Park, Kenji Watanabe, Takashi Taniguchi, Jihyun Kim, Chul-Ho Lee, Seongil Im, Gwan-Hyoung Lee. All-2D ReS2 transistors with split gates for logic circuitry. Scientific Reports. 2019, 9 (1), . https://doi.org/10.1038/s41598-019-46730-7
SAMURAI

Description:

(abstract)

Two-dimensional (2D) semiconductors, such as transition metal dichalcogenides (TMDs) and black phosphorus, are the most promising channel materials for future electronics because of their unique electrical properties. Even though a number of 2Dmaterials-based logic devices have been demonstrated to date, most of them are a combination of more than two unit devices. If logic devices can be realized in a single channel, it would be advantageous for higher integration and functionality. In this study we report high-performance van der Waals heterostructure (vdW) ReS2 transistors with graphene electrodes on atomically flat hBN, and demonstrate a NAND gate comprising a single ReS2 transistor with split gates. Highly sensitive electrostatic doping of ReS2 enables fabrication of gate-tunable NAND logic gates, which cannot be achieved in bulk semiconductor materials because of the absence of gate tunability. The vdW heterostructure NAND gate comprising a single transistor paves a novel way to realize “all-2D” circuitry for flexible and transparent electronic applications.

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Keyword: 2D semiconductors, van der Waals heterostructure, NAND gate

Date published: 2019-07-17

Publisher: Springer Science and Business Media LLC

Journal:

  • Scientific Reports (ISSN: 20452322) vol. 9 issue. 1

Funding:

  • National Research Foundation of Korea 2017R1A5A1014862
  • National Research Foundation of Korea 2018M3D1A1058793
  • National Research Foundation of Korea NRF-2017R1A2B2006568

Manuscript type: Publisher's version (Version of record)

MDR DOI:

First published URL: https://doi.org/10.1038/s41598-019-46730-7

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Updated at: 2025-02-23 22:50:28 +0900

Published on MDR: 2025-02-23 22:50:28 +0900

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