Interface-Engineered Proton-Gated Oxide Transistors with Multitimescale Synaptic Plasticity

Rupam Mandal; Kazuya Terabe; Tohru Tsuruoka

doi:10.1021/acsami.6c14036

Journal article Interface-Engineered Proton-Gated Oxide Transistors with Multitimescale Synaptic Plasticity

;

Download file (6.48 MB)
Download as zip (6.24 MB)

Collection

Citation

Rupam Mandal, Kazuya Terabe, Tohru Tsuruoka. Interface-Engineered Proton-Gated Oxide Transistors with Multitimescale Synaptic Plasticity. ACS Applied Materials & Interfaces. 2026, 18 (43), 59455-59467. https://doi.org/10.1021/acsami.6c14036

(BibTeX)

Description:

(abstract)

Ion-gated transistors that mimic biological synapses are essential for energy-efficient neuromorphic hardware capable of adaptive learning and sensory processing. However, achieving both high-speed operation and stable memory in silicon-compatible platforms remains challenging due to the trade-off between ionic mobility and retention characteristics. In this work, we developed proton-gated synaptic transistors composed of electron-beam (EB) deposited SiO2 electrolyte and sputtered WO3 channel. Low film density with oxygen deficiency of EB-deposited SiO2 enables gate-controlled proton intercalation and de-intercalation, producing versatile synaptic plasticity of continuously modulating the WO3 channel conductance. The devices exhibit a wide time response range (pulse widths from 100 ms to 50 µs) and a large dynamic range (>103) with a retention time of ~18 s, successfully emulating short-term plasticity and nociceptor-like sensory behaviors such as threshold spiking, relaxation, and sensitization. They also achieve ~90% image recognition accuracy and low power consumption of ~200 fJ for a single synaptic event. Furthermore, an introduction of a thin Al2O3 layer between the electrolyte and channel effectively suppresses proton back-diffusion, extending the retention time to ~860 s. This also results in high recognition accuracy across a wide range of pulse widths, from sub-seconds to sub-milliseconds. By integrating two transistors with different retention times into a “one-transistor–one-synapse” architecture, we further demonstrated hardware-level temporal control of synaptic plasticity that enables event-driven learning, forgetting, and memory without altering input stimuli. These results indicate that all-oxide proton-gated transistors incorporating interface engineering provide a neuromorphic platform that enables highly flexible designs with excellent synaptic characteristics.

Rights: