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[Shiho Nakamura](https://orcid.org/0009-0005-6326-7786), Zaoyang Lin, Daiki Tsuruoka, Takahiko Endo, [Xiao Yu](https://orcid.org/0000-0001-8769-521X), [Tsung-En Lee](https://orcid.org/0000-0003-1881-3539), [Yasumitsu Miyata](https://orcid.org/0000-0002-9733-5119), Nobuyuki Aoki, [Mengnan Ke](https://orcid.org/0000-0001-8235-9559)

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[Characterization of Interface States in CVD Monolayer MoS                    <sub>2</sub>                    /Al                    <sub>2</sub>                    O                    <sub>3</sub>                    MOS Capacitors via the Conductance Method](https://mdr.nims.go.jp/datasets/59fcb671-8802-453d-a2e5-480a9eab4c96)

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First Author et al.: Title 9   1 Abstract—MoS2 is one of the transition metal 2 dichalcogenides (TMDCs) that has been extensively 3 studied as a next-generation semiconductor material due 4 to its high carrier mobility in the monolayer limit. However, 5 the atomically thin nature of MoS2 poses challenges for 6 capacitance characteristics measurements by 7 metal-oxide-semiconductor (MOS) capacitors, leading to 8 limited research on the characteristics of their interfaces. 9 In this study, we fabricated MOS capacitors with different 10 device areas using a monolayer MoS2 synthesized by 11 chemical vapor deposition and Al2O3 insulator deposited 12 by atomic layer deposition and performed 13 capacitance-voltage measurements. We propose the use of 14 a ring-shaped capacitor which is beneficial for small 2D 15 crystals such as exfoliated TMDCs or materials that cannot 16 yet be synthesized on a large scale, and extracted interface 17 trap densities on the order of 1012 eV-1 cm-2 for devices with 18 different areas, indicating that under the present 19 measurement conditions, series and access resistances 20 do not dominate the extraction of interface trap density 21 using the conductance method.  22 Index Terms— conductance method, interface states, 23 metal-oxide-semiconductor capacitors, monolayer MoS2, 24 two-dimensional transition metal dichalcogenides  25 I. INTRODUCTION 26 INCE the discovery of high-performance transistors 27 based on mechanically exfoliated monolayer MoS2 [1], it 28 has become a prototypical material for two-dimensional (2D) 29 semiconductor research. Its atomically thin body, combined 30 with an optical bandgap of approximately 1.8–1.9 eV [2] and 31  This work was supported by JST, PRESTO Grant Number JPMJPR24H2, JSPS KAKENHI Grant Number 23K13361, Tokyo Electron Limited, Kenjiro Takayanagi Foundation and Iketani Science and Technology Foundation.  Shiho Nakamura, Daiki Tsuruoka and Nobuyuki Aoki are with the Department of Materials Science, Chiba University, Chiba 263-8255, Japan; Zaoyang Lin is with IMEC, Kapeldreef 75, Leuven 3001, Belgium; Takahiko Endo is with Department of Physics, Tokyo Metropolitan University, Tokyo 192-0397, Japan; Yasumitsu Miyata is with the Research Center for Materials Nanoarchitectonics, National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan; Xiao Yu is with the School of Microelectronics, Xidian University, Xi’an 710071, China; Tsung-En Lee is with Department of Microelectronics, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan; Mengnan Ke is with the SQIE Research Center, Institute for Multidisciplinary Sciences, Yokohama National University, Yokohama 240-8501, Japan; (e-mail: ke-mengnan-pv@ynu.ac.jp) reasonably high carrier mobility [3], [4], affords strong 32 electrostatic control [5], [6] and mitigates short channel effects 33 [7], [8], motivating extensive device and interface studies. 34 Conventional capacitance-voltage (C–V) measurements on 35 ultrathin 2D materials MOS capacitors [9]-[11] exhibit 36 additional frequency-dispersion arising from transverse electric 37 field distributions, parasitic capacitances, and resistance 38 associated with carrier supply from the contact electrodes and 39 lateral carrier transport in the MoS₂ region (Racc), all of which 40 complicate the accurate extraction of interface trap density (Dit) 41 [12]. Among various characterization techniques, the 42 conductance method is widely regarded as a reliable approach 43 for evaluating Dit in MOS structures [12]-[15], as it enables the 44 analysis of voltage and frequency dependence of the 45 conductance in MOS capacitors to analyze the impact of 46 interface states. In this study, we focus on establishing the 47 repeatability and reliability of the conductance method for 48 monolayer MoS2 MOS capacitors. A ring-shaped capacitor 49 geometry is introduced to obtain a sufficiently large 50 gate-modulated capacitance even from small-area 2D crystals, 51 while enabling the influence of Racc to be evaluated through the 52 diameter dependence of the C–V, C–f, and conductance 53 characteristics. This approach allows reproducible Dit 54 extraction and clarifies the measurement conditions under 55 which Racc does not dominate the conductance response.  56 II. EXPERIMENTAL 57 Figure 1(a) illustrates the fabrication process flow, while 58 Figure 1(b) and 1(c) present the schematic diagram and optical 59 micrograph of the fabricated devices, respectively. The 60 fabrication process began with the deposition of a metal gate on 61 a glass substrate. Lift-off resist, polymethyl methacrylate 62 (PMMA) A5, and Aqua Save were spin-coated to prevent 63 electron charge-up. Following electron beam lithography 64 (EBL), a 5-nm-thick Ti followed by a 10-nm-thick Pd was 65 deposited using electron beam evaporation. The lift-off process 66 was performed in N-Methyl-2-pyrrolidone. Subsequently, 67 12.4-nm-thick of Al2O3 was grown at 300°C by atomic layer 68 deposition (ALD) using trimethylaluminum and H₂O as 69 precursors. Al2O3 thickness was confirmed by spectroscopic 70 ellipsometry. The CVD-grown monolayer MoS2 was then 71 transferred onto Al2O3 using polystyrene (PS) as the carrier 72 polymer [16]. The transfer process involved spin-coating PS 73 onto the as-grown MoS2, followed by baking at 80°C for 15 74 Characterization of Interface States in CVD Monolayer MoS2/Al2O3 MOS Capacitors Via the Conductance Method Shiho Nakamura, Zaoyang Lin, Daiki Tsuruoka, Takahiko Endo, Xiao Yu, Tsung-En Lee, Yasumitsu Miyata, Nobuyuki Aoki, and Mengnan Ke S First Author et al.: Title 9 minutes to enhance adhesion. Water was introduced at the 1 interface between MoS2 and the growth substrate to initiate the 2 lift-off process. Once detached, the MoS2-PS assembly was 3 dried and transferred onto the target substrate. To improve 4 adhesion and eliminate wrinkles, the transferred MoS2 was 5 baked at 80 °C for 1 hour, followed by 150 °C for 30 minutes. 6 Finally, the PS layer was removed using toluene. After MoS2 7 transfer, PMMA A5 and Aqua Save were spin-coated for the 8 MoS2 etching process. Following patterning via EBL, the 9 samples underwent O2 plasma etching, after which the resist 10 was removed using acetone. For contact metal deposition, 11 PMMA and Aqua Save were spin-coated before patterning via 12 EBL. A 10-nm-thick In followed by a 30-nm-thick Au was 13 deposited using electron beam evaporation, followed by a 14 lift-off process in acetone. The devices were fabricated in two 15 batches using an identical fabrication process. Batch 1 16 consisted of devices with ring diameters of 10, 15, and 20 µm, 17 while Batch 2 included devices with ring diameters of 20, 30, 18 and 40 µm. The fabricated devices were annealed in a vacuum 19 at 523 K for 1 hour to improve contact properties. 20 Multi-frequency C–V and conductance measurements were 21 conducted on bottom-gated MOS capacitors using an HP 22 4824A LCR meter under vacuum at 300 K.    23  24 III. RESULTS AND DISCUSSION 25 Figure 2 shows the normalized multi-frequency forward and 26 backward C–V curves (1 MHz to 60 kHz) for devices with ring 27 diameters of 10, 15, 20 µm. 28   29 The C–f mapping in Figure 3(a) shows that the high-frequency 30 capacitance roll-off becomes more pronounced with increasing 31 device diameter, suggesting an additional RC delay associated 32 with lateral carrier supply. In contrast, the weaker and less 33 diameter-dependent dispersion observed in smaller-diameter 34 devices indicates that the influence of Racc is not dominant 35 under these measurement conditions. Therefore, the C–f 36 mapping supports the validity of the conductance-based Dit 37 extraction in the smaller-diameter devices by confirming that 38 the measured admittance response is not dominated by lateral 39 access resistance. Figure 3(b) shows a simplified equivalent 40 circuit used to illustrate the main capacitance and resistance 41 components in the measured admittance response. In the 42 depletion region, the minimum capacitance (Cmin) is 43 determined by the series combination of the depletion 44 capacitance of MoS2 (CD) and the oxide capacitance (Cox), in 45 parallel with the overlap capacitance (Cov) originating from the 46 overlap between gate and contact. The Cov does not scale with 47 the device diameter. As the ring diameter decreases, the 48 contribution of Cov to Cmin increases, which results in a 49 corresponding increase in Cmin. The apparent flat-band voltage 50 (VFB) was estimated from the linear extrapolation of the 1/C2–V 51 characteristics at 1 MHz, where C is the measured capacitance 52 after subtracting Cmin to reduce the influence of the offset 53 capacitance. The fixed charge (Qox) was then calculated (Figure 54 3(c)). The forward and backward sweeps exhibited a small VFB 55 shift (ΔVFB~0.05 V), corresponding to a charge-equivalent 56 hysteresis of ΔQox ~ 1.8×10-8 C/cm2. The extracted slow trap 57 density (ΔNst) showed ΔNst < 1.2×1011 cm-2. This minimal 58 hysteresis and small ΔNst quantitatively indicate a low density 59 of slow traps in the fabricated devices. 60  61 In this study, Cox was extracted from the C–V characteristics. In 62 the depletion region, the measured capacitance primarily 63 reflects the Cov. In the accumulation region, both Cox and Cov 64 contribute to the total measured capacitance [17]. To minimize 65 the influence of the overlap capacitance in calculating Dit, Cox 66 was defined as the difference between Cmax in accumulation and 67 Cmin in depletion measured at 60 kHz. From the obtained Cox 68 value, the dielectric constant k = Cox·d/ε0 and the equivalent 69 oxide thickness EOT = εSiO2/Cox were calculated, yielding k = 70 5.7 ± 0.4 and EOT = 8.5 ± 0.6 nm, where d is the Al2O3 71 thickness, ε0 is the vacuum permittivity, and εSiO2 = 3.9ε0. 72 Following C–V measurements, conductance measurements 73 were performed to evaluate Dit. Gp/Aωq is plotted as a function 74 of frequency for devices with ring diameters of 10, 15, 20, 30, 75 and 40 µm (Figure 4). Due to the inherently low capacitance of 76 small ring capacitors, it is challenging to obtain reliable G–f 77 curves, especially in the low-frequency region, as the signal 78 amplitude becomes comparable to the noise level of the LCR 79 meter. The measured conductance (Gm) is converted to a 80 parallel conductance (Gp) using the following relation [18]: 81  2p ox m2 2 2m ox m( )G C GA q G C Cωω ω=+ −  (1) 82 Here, Cm is the measured capacitance. Gp is normalized with 83 the area (A), frequency (ω), and charge (q). The dispersion of 84 curves indicates that a smaller device area affects both 85 capacitance and conductance measurements, especially at low 86 frequencies (Figure 4(a)). 87  Fig. 3 (a) Measured C–f mapping, (b) Simplified equivalent circuit diagram, (c) Extracted VFB and Qox for each device.  Fig. 2 Measured multi-frequency C–V characteristics for devices with the diameters of (a) 10 µm, (b) 15 µm, and (c) 20 µm.  Fig. 1 (a) Fabrication process flow for device fabrication, (b) Schematic illustration of the device structure, and (c) Optical microscopy image. First Author et al.: Title 9 Dit is calculated by using the following relation [18],  1  pitmax2.5GDA qω =    (2) 2  3 Regardless of the ring diameter, the Dit values ranged from 1012 4 to 1013 eV-1 cm-2 at the energy position of ~0.6 eV below the 5 conduction band (Figure 4(f)). The energy level of the trap 6 states was calculated using the following equation [12]: 7  th DOSexp1EkTf v Nσ∆   =  (3) 8 Here, ΔE represents the energy difference between the 9 minimum of the conduction band and the position of the Fermi 10 level. NDOS is the density of states in the conduction band per 11 unit area, and σvth denotes the carrier capture probability for a 12 trap at a specific energy level. Based on previous research [12], 13 the parameters were set as follows: NDOS=4.5×1013 cm-2, 14 vth=1.4×107 cm/s, σMoS2=10−7 cm. The Dit values were observed 15 near the conduction band and increased as they approached the 16 band edge. The extracted Dit values were consistent across 17 devices with different ring diameters (Figure 4(f)). This result, 18 together with the C–f mapping in Fig. 3(a), indicates that Racc 19 becomes detectable as a high-frequency capacitance roll-off in 20 larger-diameter devices, whereas it does not dominate the 21 conductance response used for Dit extraction under the present 22 measurement conditions. Therefore, the diameter-independent 23 Dit values confirm that the conductance method can provide 24 reliable and reproducible Dit extraction in the ring-shaped MoS2 25 MOS capacitors, while the diameter dependence of the C–f 26 characteristics provides a useful indicator of access resistance 27 related distortion. Furthermore, the results of devices with a 20 28 µm diameter fabricated in Batch 1 and Batch 2 were compared. 29 The Dit values extracted via the conductance method remained 30 consistent (Figure 4(f)). These results indicate that, although 31 there are variations in the 1L MoS2 device fabrication process, 32 such as transfer-induced variations, the conductance method 33 consistently yields reliable Dit values. This confirms the 34 applicability of this method for characterizing the interface 35 properties of Al2O3/MoS2 MOS capacitors, ensuring stable and 36 reproducible evaluation of interface trap density.  37 Finally, we compared Dit obtained from the ring capacitor 38 and FETs (Lch = 0.5 µm, 2 µm; Wch = 60 µm) (Figure 5). A good 39 agreement was observed between the ring capacitor with a 40 diameter of 20 µm and the FET with Lch = 0.5 µm. On the other 41 hand, for the FET devices, Dit increased with longer channel 42 lengths, even within the same batch, consistent with the 43 calculation in a previous study [19], which showed that the 44 channel resistance can affect accurate Dit measurements when 45 the channel length is larger than 1 μm. Moreover, for shorter Lch, 46 a larger Wch is required to achieve a sufficiently large capacitor 47 area to improve the signal-to-noise ratio, making the 48 measurement difficult when exfoliated flakes or non-large-area 49 CVD-grown crystals are used. In contrast, the ring-shaped 50 capacitor provides sufficient area for reliable C–V and 51 conductance measurements even from small-area 2D crystals, 52 and its diameter dependence enables evaluation of the effect of 53 Racc on the C–V and conductance characteristics. 54  55 The obtained Dit values (1012-1013 eV-1 cm-2) are comparable 56 to those reported for other TMDC/high-k interfaces (Table 1). 57 In addition, this study confirms the reliability and 58 reproducibility of the conductance method, indicating the 59 ring-shaped capacitor structure enables accurate Dit extraction 60 even from small-area monolayer 2D crystals. 61  62 IV. CONCLUSION 63 In this study, C–V characteristics of Al2O3/MoS2 MOS 64 capacitors with varying ring diameters of electrodes were 65 investigated. The results demonstrated that frequency 66 dispersion decreased as the device area was reduced. Dit was 67 extracted using the conductance method, and the values were 68 observed to increase near the band edge, ranging from 1012 to 69 1013 cm-2 eV-1. Notably, the extracted Dit values remained 70 consistent regardless of the electrode size, indicating that the 71 device area in the current experimental setup does not influence 72 Dit extraction. Moreover, comparison of conductance 73 measurements for devices fabricated in different batches but 74 with the same electrode area showed similar Dit values. These 75 findings confirm the reliability and repeatability of the 76 conductance method for evaluating interface states in 77 insulator/MoS2 MOS capacitors. Importantly, the ring-shaped 78 capacitor is advantageous for using small 2D crystals, such as 79 exfoliated TMDCs or materials not yet producible on a large 80 scale, making it a promising structure for extending this 81 approach to a broader class of 2D materials. We have also 82 confirmed that this method can be applied to small-area 83 exfoliated MoS2 flakes, further supporting its applicability to 84 interface-state evaluation of 2D semiconductor systems. 85  Fig. 4 Measured Gp/Aωq versus log(frequency) for MOS capacitors with ring diameters of (a) 10 µm, (b) 15 µm, (c) 20 µm, (d) 30 µm, and (e) 40 µm, (f) Extracted Dit for devices with different diameters. Table. 1 Summary of reported Dit values for TMDC/high-k interfaces. Mat. Dielectric Layers (L) Method Dit (cm-2 eV-1) ref. MoS2 Al2O3 1-L (CVD) conductance 1012-1013 this work MoS2 HfO2 1-L (CVD) conductance 1012-1013 [12] MoS2 HfO2 Few-L (exf.) CV 2×1011-2×1012 [20] WSe2 Al2O3 Multi-L (exf.) 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