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[Ryoma Hayakawa](https://orcid.org/0000-0002-1442-8230), Taiga Kijima, Yuho Yamamoto, Yoichi Yamada, [Yutaka Wakayama](https://orcid.org/0000-0002-0801-8884)

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[Reconfigurable Ternary Logic‐In‐Memory With Organic Antiambipolar Transistor](https://mdr.nims.go.jp/datasets/b0acd012-bf3f-43a6-bde0-d55aa38a96ac)

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Advanced Electronic Materials www.advelectronicmat.deRESEARCH ARTICLEReconfigurable Ternary Logic-In-Memory With Organic Antiambipolar Transistor Ryoma Hayakawa1 , 2 Taiga Kijima1 , 2 Yuho Yamamoto1 , 3 Yoichi Yamada3 Yutaka Wakayama1 1 Research Center For Materials Nanoarchitectonics (MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Japan 2 Department of Applied Chemistry, Faculty of Science and Technology, Chuo University, 1-13-27 Kasuga, Bunkyo, Japan 3 Faculty of Pure and Applied Sciences, University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Japan Correspondence: Ryoma Hayakawa ( HAYAKAWA.Ryoma@nims.go.jp) Yutaka Wakayama ( WAKAYAMA.Yutaka@nims.go.jp) Received: 30 March 2026 Revised: 29 June 2026 Accepted: 25 July 2026 Keywords: antiambipolar transistor | floating gate | logic-in-memory | reconfigurable ternary inverter ABSTRACT We developed a reconfigurable ternary logic-in-memory (LIM) device based on an organic antiambipolar transistor and incorporating a gold floating gate into a hafnium oxide (HfO2 ) gate insulator. First, a standard ternary inverter was obtained with extremely low input and drain voltages (2 V) owing to the high dielectric constant of the HfO2 gate insulator. Three distinct output logic states (“2,” “1,” and “0”) were clearly obtained for the corresponding input logic states (“0,” “1,” and “2”). Then, the voltage transfer curve was laterally shifted up to 1.8 V by controlling the hole- and electron-injection processes into the floating gate, obtaining a ternary nonvolatile memory. This memory function realized versatile reconfigurable ternary inverter operations. Three ternary inverters, namely, standard, negative, and positive ternary inverters, were demonstrated in a single LIM device. Remarkably, these inverter operations were performed using the same input voltages and then electrically reconfigured by adjusting the charge condition (i.e., holes or electrons) of the floating gate. Our development seems promising for performing multivalued in-memory computing toward surpassing the capabilities of existing von Neumann systems. 1T  (  o  g  f  [  w  r  d  o  d  s  b               To©Ah Introduction he development of high-performance organic integrated circuitsICs) is gaining increasing attention owing to the emergencef edge artificial intelligence and Internet-of-Things systemsiven the benefits of organic materials, including mechanicallexibility, light weight, low-cost production, and biocompatibility 1–5 ]. Many efforts have been devoted to interactive mobile andearable applications, with representative examples includingadiofrequency identification tags, wearable displays, securityevices, and healthcare sensors [ 6–10 ]. In such applications,rganic ICs are often used as flexible amplifiers and analog-to-igital converters for real-time processing of signals from versatileensors and actuators. However, organic ICs remain constrainedy their low integration density and poor processing owing tohis is an open access article under the terms of the Creative Commons Attribution Licenriginal work is properly cited. 2026 The Author(s). Advanced Electronic Materials published by Wiley-VCH GmbH dvanced Electronic Materials , 2026; 12:e70538 ttps://doi.org/10.1002/aelm.70538incompatibility with conventional lithography techniques [ 1–4 ].The typical integration density of organic transistors remains aslow as ∼ 100 transistors per cm2 [ 1, 4, 5 ]. Although relativelyhigh integration densities of up to ∼ 1500 transistors per cm2 havebeen demonstrated using specific photolithography techniques,such examples remain limited [ 11–13 ]. Therefore, exploring newstrategies beyond the miniaturization of electronic components isrequired for the advancement of organic ICs. Multivalued logic circuits (MVLs) constitute promising alter-natives to existing binary logic circuits owing to their highintegration density, low power consumption, and high-speedoperation. Recently, various types of MVLs have been demon-strated with diverse semiconductor materials including organicsemiconductors [ 14–20 ]. Moreover, the circuit complexity ofse, which permits use, distribution and reproduction in any medium, provided the 1 of 9http://www.advelectronicmat.dehttps://doi.org/10.1002/aelm.70538https://orcid.org/0000-0002-1442-8230https://orcid.org/0000-0002-0801-8884mailto:HAYAKAWA.Ryoma@nims.go.jpmailto:WAKAYAMA.Yutaka@nims.go.jphttp://creativecommons.org/licenses/by/4.0/https://doi.org/10.1002/aelm.70538http://crossmark.crossref.org/dialog/?doi=10.1002%2Faelm.70538&domain=pdf&date_stamp=2026-08-20e  i  e  f  c  i  t  MA  (  l  b  k  n  c  t  e  M  r  a  aI  a  i  i  an  d  i  c  h  s  I  iF  t  (  k  l  S  u  e  i v  o  a  e  L  t  b  t  r  l  s  M  w  t                                               2 2199160x, 2026, 19, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.70538 by National Institute For, Wiley Online Library on [14/10/2026]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicablexisting binary logic circuits can be drastically reduced byntroducing MVLs. For example, the reduction area in ICs isxpected to reach 35% for ternary logic circuits and above 50%or quaternary logic circuits [ 14, 19, 21 ]. Such reductions in theircuit area and number of interconnectors can contribute tomproving the processing speed and power consumption. Overall,he potential advantages can foster the development of organicVLs for next-generation computing architectures.  remarkable alternative is the adaptation of the logic-in-memoryLIM) architecture [ 22–26 ]. In current von Neumann systems,ogic and memory components are physically isolated, increasingoth power consumption and data latency. These obstacles,nown as von Neumann bottlenecks, become increasingly promi-ent due to the intensive data transfer between logic and memoryomponents in modern devices [ 27, 28 ]. In the LIM architecture,he logic and memory components are merged in the same circuit,nabling high-throughput and energy-efficient data processing.oreover, the incorporation of nonvolatile memory enableseconfigurable logic operations. Like field-programmable gaterrays, individual logic circuits can be electrically reconfiguredt the hardware level [ 29–31 ]. n this study, we developed a ternary LIM device based onn organic antiambipolar transistor (OAAT), where the ternarynverter and ternary nonvolatile memory functions are combinedn the same device. An AAT is a heterojunction transistor witht least a p–n junction in the transistor channel [ 32–39 ]. This p– junction induces negative differential transconductance. Therain current increases and then decreases despite the monotonicncrease in gate voltage. Therefore, AATs exhibit Λ- or N-shapedurrent transfer curves, which have been leveraged in MVLs. Weave demonstrated ternary and quaternary logic circuits via theeries connection of an OAAT and n-type transistors [ 40–43 ].n this study, we further introduced a gold (Au) floating gate tontegrate a nonvolatile memory function into a ternary inverter. irst, the prepared ternary LIM device behaves as a standardernary inverter (STI) with extremely low input ( Vin ) and drain VD ) voltages of 2 V owing to its hafnium oxide (HfO2 ) high- gate insulator. Three output voltages ( Vout ) corresponding toogic states “2,” “1,” and “0” are observed while sweeping Vin .ubsequently, the voltage transfer curve is markedly shiftedp to 1.8 V by adjusting the type of carrier (i.e., holes orlectrons) trapped in the floating gate. This feature allows thenverter to work as a ternary nonvolatile memory. Three Voutalues representing logic states “2,” “1,” and “0” are clearlybserved at the reading input voltage ( Vin , read ) of 0.5 V, evenfter turning off the supplied voltages. This memory functionnables reconfigurable ternary inverter operations in a singleIM device. Three typical ternary inverters, namely, STI, negativeernary inverter (NTI), and positive ternary inverter (PTI) cane electrically reconfigured by controlling hole- and electron-rapping processes into the floating gate. These functions areequired to construct the combined systems of ternary and binaryogic circuits, where ternary signals are converted to binaryignals and vice versa, leading to the realization of more advancedVLs, e.g., ternary decoders, adders, and two-input logic circuits,ith smaller footprints [ 14, 26 ]. Our approach thus paves the wayo high-performance flexible and wearable organic ICs in future. of 9 2 Results and Discussion 2.1 STI Operation Figure 1a,b shows the device structure and optical microscopeimage of the developed ternary LIM device. The correspondingequivalent circuit is depicted in Figure 1c . The ternary inverterpart is constructed by a series circuit comprising an OAAT andan n-type transistor via an output electrode. In addition, 7-decyl-2-phenyl[1]benzothieno[3,2- b ][1]benzothiophene (Ph-BTBT-C10 )and PhC2 H4 -benzo[de]isoquinolino[1,8-gh]quinolone diimide(PhC2 -BQQDI) films are used as the p- and n-type organicsemiconductors, respectively. The source electrode is formedon the PhC2 -BQQDI channel layer, while the drain electrodeis formed on the Ph-BTBT-C10 channel layer. Additionally,an Au bottom gate electrode is used as the common inputelectrode of the inverter. Another Au film sandwiched betweentwo HfO2 layers constitutes the floating gate to integrate thenonvolatile memory function into the ternary inverter. Thetop and bottom HfO2 layers serve as the tunneling and gateinsulating layers, respectively. The detailed preparation ofthe ternary LIM and optimization of the device structure areprovided in the experimental section and supporting information(Figures S1–S3 ). Figure 1d exhibits the current transfer of drain current ( ID ) − gatevoltage ( VG ) for the OAAT and PhC2 -BQQDI transistor in aternary LIM device. VD values of 2 and − 2 V were applied to thePhC2 -BQQDI transistor and OAAT, respectively. As the floatinggate was grounded before measuring the current transfer curves,no charges appeared in the floating gate. The VG values for the cor-responding transistors are allocated from the common Vin values.Given the equivalent circuit in Figure 1c , Vin is directly appliedto the PhC2 -BQQDI transistor as the gate voltage ( VG, PhC2-BQQDI ).Conversely, voltage difference ( Vin − VD ) is supplied as theOAAT gate voltage ( VG, AAT ). The PhC2 -BQQDI transistor exhibitsa typical n-type operation. ID in the transistor monotonicallyincreases with Vin (blue line in Figure 1d ). Meanwhile, the OAATindicates a horizontally flipped N-shaped current transfer curveaccording to Vin because ( Vin − VD ) is applied to the OAAT asVG, AAT (red line in Figure 1d ). First, ID in the OAAT decreaseswith Vin and then starts increasing at Vin of 0.8 V. Afterward, ID reduces again at Vin of 1.3 V and is completely suppressed at Vin of 1.8 V. The corresponding voltage transfer curve ( Vout–Vin ) of the ternaryLIM device for VD of 2 V is shown in Figure 1e . Three differentVout values are observed at 2.0, 0.9, and 0 V with increasing Vin ,corresponding to logic Vout states “2,” “1,” and “0,” respectively.This response corresponds to the typical STI operation. Thechange in Vout in the ternary LIM device can be explained byconsidering ID variations of both constituent transistors accordingto the common Vin (Figure 1d ). The ID–VG curves shown in Figure 1d can be divided into threeVin ranges (green dashed lines). In range (i) ( Vin < 0.8 V), ahigher ID flows in the OAAT compared with that of the PhC2 -BQQDI transistor. Accordingly, VD of 2.0 V is the highest Vout (logic state “2”) in range (i) in Figure 1e because the outputand drain electrodes are electrically connected. Then, comparableAdvanced Electronic Materials, 2026Creative Commons LicenseFIGURE 1 (a) Device structure and (b) optical microscope image of ternary LIM with Au floating gate. PhC2 -BQQDI and Ph-BTBT-C10 films are used as transistor channels. (c) Equivalent circuit of ternary LIM device constructed by a series circuit comprising OAAT and n-type transistor. (d) ID –VG curves of OAAT and n-type transistor in ternary LIM device. The VG values for respective transistors are converted from Vin of the ternary LIM device. (e) Vout–Vin curve of ternary LIM device, where Vin intervals (i), (ii), and (iii) agree with Vout ranges of logic states “2,” “1,” and “0,” respectively. (f) Butterfly curve of ternary LIM device. I  1  s  O  P  H  s  “  t  (  d  g  f  s  c  m  w  F  i  T  iF a  t                    A 2199160x, 2026, 19, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.70538 by National Institute For, Wiley Online Library on [14/10/2026]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable CreatD values flow in both transistors in range (ii) (0.8 < Vin <.2 V) (Figure 1d ). Hence, Vout of 0.9 V is obtained as logictate “1” (Figure 1e ). Further increasing Vin reduces ID in theAAT in range (iii) ( Vin > 1.2 V) (Figure 1d ), whereas ID in thehC2 -BQQDI transistor increases with increasing Vin (Figure 1d ).ence, a conducting path is formed between the output andource electrodes, resulting in the lowest Vout (0 V) as logic state0” (Figure 1e ). Therefore, the full Vout swing from VD (2 V) tohe ground voltage (0 V) is obtained in the voltage transfer curveFigure 1e ). Moreover, STI operation is achieved at extremely lowriven voltages ( Vin and VD of 2 V) owing to the HfO2 high- kate insulator. Usually, operation voltages above 5 V are requiredor ternary inverter operation [ 34–37, 40–42 ]. Additionally, highertatic noise margins (SNMs) are obtained in our LIM device,ompared with those of the reported ternary inverters [ 35, 41 ]. Theaximum and averaged SNMs obtained from 10 different devicesere estimated at 0.4 and 0.3 ± 0.1 V, respectively (Figure 1f ;igure S2 ). These values correspond to 80% and 60% of thedeal value of the ternary inverter ( VD /4 = 0.5 V), respectively.herefore, the obtained low-voltage STI operation with high SNMs a remarkable achievement in this study. igure 2a,b shows the actual STI operation, where Vin and Voutre measured over time. When 0, 1.0, and 2.0 V are assigned ashe lowest (i.e., logic state “0”), middle (i.e., logic state “1”), anddvanced Electronic Materials, 2026highest (i.e., logic state “2”) Vin states, the corresponding Vout values of 2.0, 0.8, and 0 V are obtained as the highest (i.e., logicstate “2”), middle (i.e., logic state “1”), and lowest (i.e., logic state“0”) Vout states, respectively (Figure 2a ). Stable STI operation isconfirmed for the repeated application of Vin signals, as shown inFigure 2b . 2.2 Ternary Nonvolatile Memory Operation We present the nonvolatile memory operation in the ternary LIMdevice by controlling the charge condition of the Au floating gate.The initial, electron- and hole-trapped processes are illustrated inFigure 3a . The carrier injection processes into the floating gateare affected by the film thickness of the HfO2 tunneling layer andpre-voltage application conditions. Therefore, we optimize theseparameters before evaluating the memory properties, as shownin Figures S3 and S4 . The detailed carrier-injection mechanisminto the Au floating gate is provided in Supporting Information.The electron injection into the Au floating gate occurs from thesource electrode via the PhC2 -BQQDI layer when a positive Vin isapplied. In contrast, holes are injected into the floating gate whena negative Vin is applied. Both carrier-injection currents followFowler-Nordheim tunneling, which is the same analogy as thosein conventional floating-gate memories. 3 of 9ive Commons LicenseFIGURE 2 STI operations in ternary LIM device with (a) single and (b) repeated Vin signals. Labels (i) and (ii) indicate changes in Vin and Vout over time, respectively. Three different Vout states (i.e., logic states “2,” “1,” and “0”) are observed for the corresponding Vin states (i.e., logic states “0,”“1,” and “2”). I  c  T  F  T  p  e  t  V  v  V  H  s  d  s  V  t  (  (  1  t  t  S  l  a  gT  f  m  “  T  s  t  T  i  s                           4 2199160x, 2026, 19, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.70538 by National Institute For, Wiley Online Library on [14/10/2026]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Crean the initial process, the Au floating gate is grounded, and noharges are accumulated in that gate (stage (i) in Figure 3a ).herefore, a similar voltage transfer curve to that shown inigure 1e appears at the initial state (black line in Figure 3b ).hen, Vin of − 5.5 V is applied for 30 s as the pre-voltageulse to the input electrode to trap holes in the floating gate,stablishing a hole-trapping process (stage (ii) in Figure 3a ). Inhis stage, the voltage transfer curve laterally shifts toward lowin values (red line in Figure 3b ). This is because the thresholdoltages ( Vth ) of both constituent transistors are shifted to lowin values by the trapped holes in the floating gate (Figure S6a ).ence, the center position of the middle Vin state (i.e., logictate “1”) varies from 0.5 V (black dotted line) to − 0.4 V (redotted line), as shown in Figure 3b . Meanwhile, the oppositehift in the voltage transfer curve is induced by a pre-voltagein of 5.5 V applied for 20 s (blue line in Figure 3b ) owingo the electron-trapping process into the floating gate (stageiii) in Figure 3a ). The center position of the middle Vin statei.e., logic state “1”) changes from 0.5 V (black dotted line) to.4 V (blue dotted line) (Figure 3b ). This variation in the voltageransfer curve with the electron-trapping process coincides withhreshold voltage shifts in both constituent transistors (Figure6b ). Remarkably, the entire shift in the middle Vin state (i.e.,ogic state “1”), namely, the memory window, reaches 1.8 V bydjusting the electron- and hole-trapping processes in the floatingate. his marked shift in the voltage transfer curve induced by theloating gate allows the device to operate as a ternary nonvolatileemory. Three distinct Vout states that correspond to logic states0, ” “1, ” and “2” are observed by monitoring at Vin , read of 0.5 V.he individual Vout states are continuously output for at least 3500, as shown in Figure 3c . The switching property between thehree Vout states in the ternary memory is depicted in Figure 3d .he three Vout states are clearly distinguishable. The deviationsn Vout values at corresponding logic states “0, ” “1,” and “2” aremall and estimated to be within 0.2 V. of 92.3 Reconfigurable Ternary LIM Operation Based on the abovementioned developments, namely, ternaryinverter and ternary memory operations in the same device, wedemonstrate representative reconfigurable ternary LIM opera-tions (Figure 4 ). Three distinct inverter operations, namely, STI,NTI, and PTI, are obtained by controlling the charge conditionof the floating gate. These inverters are necessary to constructternary logic circuits, e.g., ternary decoders, adders, and two-input logic circuits, where ternary signals are converted to binarysignals and vice versa [ 26, 44, 45 ]. The truth table of the individual ternary inverters is depicted inFigure 4a . Figure 4b shows the STI, NTI, and PTI operations atthe initial, hole-trapped, and electron-trapped states, respectively.Importantly, the three inverter operations are achieved for thesame Vin sequence. At the initial state, the device exhibitsnormal STI operation. For Vin logic states “0,” “1,” and “2,” theopposite Vout logic states, namely, “2,” “1,” and “0,” are obtained,respectively (stage (i) in Figure 4b ). At the hole-trapped state,Vout logic states “2,” “0,” and “0” are output for the same Vin sequence as that of the initial state ( Vin logic states of “0,” “1,”and “2,” respectively) (stage (ii) in Figure 4b ). Hence, the circuitvaries from STI to NTI by the transition from the initial to thehole-trapped state. Finally, the device operates as PTI at theelectron-trapped state. Vout logic states “2,” “2,” and “0” are visiblewithout any variation in the Vin sequence (stage (iii) in Figure 4b ).Stable inverter operations in STI, NTI, and PTI are confirmed forover 10 repeated Vin sequences, as shown in Figure 4c . Similarly, different ternary inverter operations corresponding tothe derivatives of NTI and PTI can be demonstrated with the sameVin sequence, as shown in Figure 5 , where Vout logic states “2,” “1,”and “0” (STI, initial state), Vout logic states “1,” “0,” and “0” (NTI2, hole-trapped state), and Vout logic states “2,” “2,” and “1” (PTI2, electron-trapped state) are obtained at Vin of − 0.4, 0.5, and 1.5 Vrepresenting logic states “0,” “1,” and “2,” respectively. Advanced Electronic Materials, 2026tive Commons LicenseFIGURE 3 (a) (i) Initial, (ii) hole-trapping, and (iii) electron-trapping processes of ternary LIM device. (b) Vout–Vin curves obtained at initial (black line), hole-trapped (red line), and electron-trapped (blue line) states. The dotted black, red, and blue lines are drawn at the center positions of the middle Vin state (i.e., logic state “1”) measured at the initial, hole-trapped, and electron-trapped states, respectively. (c) Retention property of ternary LIM device measured at Vin, read of 0.5 V. (d) Switching property of ternary LIM device. The switching behavior is measured at Vin, read of 0.55 V through the following pre-voltage pulse sequence: initial state ( Vin = 0 V, grounded)→ hole-trapped state ( Vin = − 5.5 V for 30 s)→ hole-erased state ( Vin = 5.0 V for 10 s)→electron-trapped state ( Vin = 5.5 V for 20 s)→ electron-erased state ( Vin = − 5.0 V for 10 s). A  t  a  l  L  c  m  t         A 2199160x, 2026, 19, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.70538 by National Institute For, Wiley Online Library on [14/10/2026]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creats shown above, our LIM device enables electrical reconfigura-ion between STI, NTI, and PTI with only two transistors (OAATnd an n-type transistor). Besides, the operation voltages are asow as 2 V for all ternary inverter operations. Similar ternaryIM operations have been demonstrated with versatile materialombinations with not only organic materials, but also inorganicaterials (Table 1 ) [ 26, 42, 44–47 ]. However, in most cases, thehree ternary inverters are formed by different circuit designsdvanced Electronic Materials, 2026and thus cannot be reconfigured in general [ 44, 45 ]. Besides,3–6 transistors are required to realize the STI operation usingconventional transistors [ 19, 48–50 ]. Although there is only anexample of the complete transition of STI, NTI, and PTI usingan organic AAT, the driving voltage of as high as 6 V and theprograming voltage of up to 18 V are necessary [ 26 ]. Therefore,our proposed LIM device has superior potential to realize furtherenergy-efficient computing systems in future. 5 of 9ive Commons LicenseFIGURE 4 (a) Truth table of ternary inverters: STI, NTI, and PTI. (b) Reconfigurable ternary inverter operations of (i) STI, (ii) NTI, and (iii) PTI achieved at initial, hole-trapped, and electron-trapped states, respectively, for the same Vin sequence. (c) Repeated ternary inverter operations of (ii) STI, (iii) NTI, and (iv) PTI for the same (i) Vin sequence. FIGURE 5 (a) Truth table of ternary inverters STI, NTI 2, and PTI 2. NTI 2 and PTI 2 are the derivatives of NTI and PTI shown in Figure 4 , respectively. (b) Reconfigurable ternary inverter operations: (i) STI (initial state), (ii) NTI 2 (hole-trapped state), and (iii) PTI 2 (electron-tapped state). (c) Repeated ternary inverter operations of (ii) STI, (iii) NTI, and (iv) PTI for the same (i) Vin sequence. 6 of 9 Advanced Electronic Materials, 2026 2199160x, 2026, 19, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.70538 by National Institute For, Wiley Online Library on [14/10/2026]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons LicenseTABLE 1 Comparison in ternary inverters with STI, NTI, and PTI operations. Type Material Number of transistors in STI/NTI/PTI STI operation voltage (V) Reconfigurable operation Memory type Memory window (V) Refs. Si-FinFET/RRAM Si-FinFET 6/2/2 ∼ 1 No HfO2 -based RRAM ∼ 1 [ 44 ] Si-FinFET/MRAM Si-FinFET 6/2/2 ∼ 1 No STT-MRAM NA [ 45 ] 2D-AAT ReS2 /BP 2/NA/NA 6 No 2D-floating fate ∼ 1 [ 46 ] Organic AAT PTCDI- C13 /DNTT 2/NA/NA 5 No Metal floating gate (Al) ∼ 3 [ 47 ] Organic AAT PTCDI- C13 /DNTT 2/2/2 6 Yes Metal floating gate (Al) ∼ 2 [ 26 ] Organic AAT (our previous work) PhC2 -BQQDI/C8 - BTBT 2/NA/NA 10 No Polymer floating gate (ZnPc-PS4 ) ∼ 2 [ 42 ] Organic Aat (in this work) PhC2 -BQQDI/Ph- BTBT-C10 2/2/2 2 Yes Metal floating gate (Au) ∼ 2 3W  o  a  F  a  f  c  t  v  t  r  d  S  i  c  S  a  s44A  a  a  e  c  N  l  d                         A 2199160x, 2026, 19, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.70538 by National Institute For, Wiley Online Library on [14/10/2026]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creat Conclusion e demonstrated a reconfigurable ternary LIM device consistingf an OAAT and n-type transistor. An Au floating gate playedn important role in reconfigurable ternary logic operations.irst, a normal STI was obtained at low driven voltages of 2 Vt the initial state. Furthermore, NTI and PTI were obtainedor the same Vin signal as that of STI by adjusting the chargeondition of the floating gate. Importantly, these reconfigurableernary inverters were prepared with an extremely low operatingoltage of 2 V and with only two transistors (OAAT and n-typeransistor). Additionally, ternary inverter operations cannot beeconfigured in general. In contrast, our proposed ternary LIMevice achieved versatile ternary inverter operations, includingTI, NTI, and PTI, with only two transistors. Furthermore, thesenverters were electrically reconfigured by controlling the chargeondition of the floating gate without variations in the Vin signals.uch functions can support the development of reconfigurablend energy-efficient artificial intelligence systems, aiming aturpassing existing von Neumann systems.  Experimental Section/Methods .1 Formation of Ternary LIM  ternary LIM with an Au floating gate was prepared on highly doped p-type Si (100) substrate ( < 0.01 Ω⋅cm) with 200 nm-thick SiO2 film. First, an Au (30 nm)/Cr (5 nm)lectrode was deposited as a common input electrode of theircuit on an SiO2 /Si substrate via thermal vacuum deposition.ext, an HfO2 film (35 nm) was formed as the gate insulatingayer of the OAAT and n-type transistor using atomic layereposition (SUGA, SAL 1000) at a substrate temperature ofdvanced Electronic Materials, 2026175◦C. Tetrakis(dimethylamino)hafnium and water were usedas the hafnium and oxygen sources, respectively. Then, an Au(10 nm)/Cr (5 nm) electrode was thermally grown on the HfO2 gate insulating layer as the floating gate at a deposition rate of 5Å/s to ensure a smooth surface morphology of the Au thin film.Subsequently, an 8 nm-thick HfO2 tunneling layer was formedvia atomic layer deposition following the same process as thatfor the gate insulating layer. To passivate carrier trap sites on theHfO2 surface, a 10 nm-thick polystyrene (Sigma–Aldrich, 182427;average molecular weight, 280,000) layer was spin-coated on theHfO2 tunneling layer. Next, Ph-BTBT-C10 (17 ± 2 nm) and PhC2 -BQQDI (23 ± 2 nm) films were grown as p- and n-type organictransistor channels, respectively, via thermal vacuum depositionat a background pressure of 10− 7 Pa. Finally, 30 nm-thick Aufilms were deposited for the source, drain, and output electrodesvia thermal vacuum deposition. The typical channel lengths andwidths of the OAAT were 107 ± 11 and 228 ± 11 µm, respectively,and those of the n-type transistor were 304 ± 6 and 334 ± 14 µm,respectively. 4.2 Electrical Measurement of Ternary LIM The electrical measurements of the ternary LIM were performedusing source measurement units (Keysight Technologies, B2912B)at room temperature. All measurements were conducted usinga four-probe system at room temperature under atmosphericconditions. Acknowledgements This research was supported by Research Center for Materials Nanoar-chitectonics (MANA) of National Institute for Materials Science (NIMS),7 of 9ive Commons LicenseT  2  o  A  A  i  e  JCTDT  sR SN  02  B  A  o3  E  64  S  P  M5  I  (6  p  DA  a7  S  M8  H  t9  a  S  h1  p  11  P  T  h1  R  T  h                                            8 2199160x, 2026, 19, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.70538 by National Institute For, Wiley Online Library on [14/10/2026]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creatsukuba, Japan, and JSPS Kakenhi grant numbers 19H00866 and3H00269, the Canon Foundation, the Innovative Science and Technol-gy Initiative for Security of the Acquisition, Technology & Logisticsgency (ATLA), Ministry of Defense grant number JPJ004596, anddvanced Research Infrastructure for Materials and Nanotechnologyn Japan (ARIM) of the Ministry of Education, Culture, Sports, Sci-nce and Technology (MEXT) grant numbers JPMXP1224NM5158 andPMXP1225NM5099. onflicts of Interest he authors declare no conflicts of interest. ata Availability Statement he data that supports the findings of this study are available in theupplementary material of this article. eferences 1 . P. A. Ersman, R. Lassnig, J. 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Tay, “Design andImplementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials,” Applied Sciences 9 (2019): 4212, https://doi.org/10.3390/app9204212 . Supporting Information Additional supporting information can be found online in the SupportingInformation section. Supporting File : aelm70538-sup-0001-SuppMat.docx. 9 of 9le Creative Commons Licensehttps://doi.org/10.1109/TED.2021.3130565https://doi.org/10.1038/s41928-018-0092-2https://doi.org/10.1002/aelm.202100167https://doi.org/10.1002/aelm.202200783https://doi.org/10.1002/adma.201808265https://doi.org/10.1002/smll.202103365https://doi.org/10.1002/aelm.201700106https://doi.org/10.1002/adma.202201277https://doi.org/10.1002/adma.202109491https://doi.org/10.1002/admi.202201857https://doi.org/10.1021/acs.nanolett.8b01357https://doi.org/10.1039/D1TC05858Dhttps://doi.org/10.1021/acs.nanolett.2c04415https://doi.org/10.1002/adfm.202213899https://doi.org/10.1109/ACCESS.2022.3211562https://doi.org/10.1016/j.rineng.2025.104011https://doi.org/10.1002/adfm.201909645https://doi.org/10.1049/iet-cdt.2019.0216https://doi.org/10.1002/aelm.202500221https://doi.org/10.3390/app9204212 Reconfigurable Ternary Logic-In-Memory With Organic Antiambipolar Transistor 1 | Introduction 2 | Results and Discussion 2.1 | STI Operation 2.2 | Ternary Nonvolatile Memory Operation 2.3 | Reconfigurable Ternary LIM Operation 3 | Conclusion 4 | Experimental Section/Methods 4.1 | Formation of Ternary LIM 4.2 | Electrical Measurement of Ternary LIM Acknowledgements Conflicts of Interest Data Availability Statement References Supporting Information