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Joaquin Santandera, Iñigo Martin-Fernandez, Carlos Carbonell, Alex Rodríguez-Iglesias, Laura Fuentes-Rodríguez, Marta Fernández-Regúlez, Llibertat Abad, Aitor F. Lopeandia, Arindom Chatterjee, Nini Pryds, Luis Fonseca, Marc Salleras

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Microsoft Word - AMO_TSTA_A_2665920.docxScience and Technology of Advanced MaterialsISSN: 1468-6996 (Print) 1878-5514 (Online) Journal homepage: www.tandfonline.com/journals/tsta20A novel approach to micro-fabricatedthermoelectric generators with SrTiO3Joaquin Santander, Iñigo Martin-Fernandez, Carlos Carbonell, AlexRodríguez-Iglesias, Laura Fuentes-Rodríguez, Marta Fernández-Regúlez,Llibertat Abad, Aitor F. Lopeandia, Arindom Chatterjee, Nini Pryds, LuisFonseca & Marc SallerasTo cite this article: Joaquin Santander, Iñigo Martin-Fernandez, Carlos Carbonell, AlexRodríguez-Iglesias, Laura Fuentes-Rodríguez, Marta Fernández-Regúlez, Llibertat Abad, AitorF. Lopeandia, Arindom Chatterjee, Nini Pryds, Luis Fonseca & Marc Salleras (08 May 2026):A novel approach to micro-fabricated thermoelectric generators with SrTiO3, Science andTechnology of Advanced Materials, DOI: 10.1080/14686996.2026.2665920To link to this article:  https://doi.org/10.1080/14686996.2026.2665920© 2026 The Author(s). Published by NationalInstitute for Materials Science in partnershipwith Taylor & Francis Group.View supplementary material Accepted author version posted online: 08May 2026.Submit your article to this journal View related articles View Crossmark dataFull Terms & Conditions of access and use can be found athttps://www.tandfonline.com/action/journalInformation?journalCode=tsta20https://www.tandfonline.com/journals/tsta20?src=pdfhttps://www.tandfonline.com/action/showCitFormats?doi=10.1080/14686996.2026.2665920https://doi.org/10.1080/14686996.2026.2665920https://www.tandfonline.com/doi/suppl/10.1080/14686996.2026.2665920https://www.tandfonline.com/doi/suppl/10.1080/14686996.2026.2665920https://www.tandfonline.com/action/authorSubmission?journalCode=tsta20&show=instructions&src=pdfhttps://www.tandfonline.com/action/authorSubmission?journalCode=tsta20&show=instructions&src=pdfhttps://www.tandfonline.com/doi/mlt/10.1080/14686996.2026.2665920?src=pdfhttps://www.tandfonline.com/doi/mlt/10.1080/14686996.2026.2665920?src=pdfhttp://crossmark.crossref.org/dialog/?doi=10.1080/14686996.2026.2665920&domain=pdf&date_stamp=08%20May%202026http://crossmark.crossref.org/dialog/?doi=10.1080/14686996.2026.2665920&domain=pdf&date_stamp=08%20May%202026https://www.tandfonline.com/action/journalInformation?journalCode=tsta20A novel approach to micro-fabricated thermoelectric generators with SrTiO3 Joaquin Santandera, Iñigo Martin-Fernandeza, Carlos Carbonella, Alex Ro-dríguez-Iglesiasa, Laura Fuentes-Rodrígueza, Marta Fernández-Regúleza, Llibertat Abada, Aitor F. Lopeandiab,c, Arindom Chatterjeed, Nini Prydsd, Luis Fonsecaa, and Marc Sallerasa* aInstitute of Microelectronics of Barcelona (IMB-CNM-CSIC), 08193 Bellaterra, Spain. bPhysics Department, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain. cGTNAM at Institut Català de Nanociència i Nanotecnologia (ICN2), 08193 Bellaterra, Spain. dDepartment of Energy Conversion and Storage, Technical University of Denmark, 2800 Kgs Lyngby, Denmark. *marc.salleras@csic.esACCEPTED MANUSCRIPTPublisher: Taylor & Francis & The Author(s). Published by National Institute for Materials Science in partnership with Taylor & Francis Group. Journal: Science and Technology of Advanced MaterialsDOI: 10.1080/14686996.2026.2665920 https://crossmark.crossref.org/dialog/?doi=10.1080/14686996.2026.2665920&domain=pdf  A novel approach to micro-fabricated thermoelectric generators with SrTiO3 The growing demand for autonomous, sustainable, and delocalized power sources for low-power-consuming electronic devices is driving a significant research ef-fort on energy harvesting technologies. Among these, micro-thermoelectric gen-erators (µTEGs) emerge as an appealing solution because of the abundance of re-sidual latent heat sources. This paper proposes an approach to combine high-performance thermoelectric oxides with Si-based µTEGs, leveraging the minia-turization and high-density integration of CMOS-like technologies. The approach is applied to the integration of niobium doped strontium titanate (Nb:STO) thin films on Si-based planar µTEG structures. The Nb:STO-based µTEG achieves a specific power density Γ = 0.36 nW·cm-²·K-² under controlled temperature gradi-ents, which is below state-of-the-art performance probably due to lower electrical conductivity from polycrystalline growth. When the chips were tested under real-istic operating conditions—placed on a hot surface at 175 °C—a maximum pow-er output of P = 0.07 nW was obtained. Nonetheless, by implementing a techno-logical solution for thermal dissipation, the temperature gradient across the ther-moelectric material improved by a factor of 110, resulting in a significantly high-er extracted power of P = 7.75 nW. Keywords: thermoelectric; micro-thermoelectric generator; thin-films; SrTiO₃; IoT; Subject classification codes: 105; 210; 306; 206; 208.  Introduction Thermal sources such as automotive engines, industrial processes, and home heating generate enormous amounts of waste heat [1] that could be converted into useful energy if efficient low-temperature thermal energy harvesters were available [2–4]. In this frame, thermoelectric generators (TEGs), solid state devices that convert heat (some temperature difference) into electric energy, become an attractive solution to self-powered electronic systems and as a sustainable alternative to conventional batteries, reducing the reliance on critical raw materials (CRM) in energy-related technologies. ACCEPTED MANUSCRIPT  TEGs are of particular interest to power devices that are delocalised, or whenever acces-sibility to replace the batteries is challenging, for example, in Internet of Things (IoT) networks and harsh environments, such as industrial reactors, power stations and volca-noes [5–10]. The thermoelectric efficiency of a material is expressed by the dimensionless figure of merit zT:   𝑧𝑇= 𝑇 (1) where S is the Seebeck coefficient, σ is the electrical conductivity, κ is the thermal con-ductivity, and T is the temperature. The materials with the highest zT in the low and intermediate temperature ranges (from 300 K to 600 K [9]) are typically based on scarce and toxic elements, such as tellurium and lead. In addition, the fabrication of the related TEG faces limitations for mass production and miniaturization that hinder integration and deployment with mass-produced electronic devices like the nodes in IoT networks [11]. Consequently, current research in thermoelectric materials focuses on balancing performance with sustainability by using more abundant and low-toxicity materials such as Half-Heusler alloys, lead-free chalcogenides, silicides, perovskites, and organic thermoelectrics [12], on novel technological solutions for the TEGs to better conform to the heat surfaces to optimise thermal efficiency at the device level and to unlock new uses, and on enabling mass production.  In the latter case, TEG technologies based on a modest zT material like Si benefit from miniaturisation, scalability and efficiency in the use of materials provided by semiconductor micro- and nanotechnologies (MNTs) [10,13–15]. MNTs enable optimising the architecture of the micro-TEG (µTEG) and implementing thermal engineering to maximise the temperature difference across the thermoelectric material that critically determine the device  performance, ZT [16–19]. It ACCEPTED MANUSCRIPT  has been demonstrated how this approach can provide output powers well within the range of IoT needs [20–23].  The thermoelectric efficiency of a TEG is expressed by the dimensionless figure of merit ZT:   𝑍𝑇= 𝑇 (2) where G is the electrical conductance, and K is the thermal conductance, and T is the temperature. Here, it needs to be noted that ZT [17] is critically determined by the device architecture and thermal engineering at device level, which serve at maximizing the temperature difference across the thermoelectric material. In this work, we demonstrate a multiscale approach to explore the integration of novel thin-film thermoelectric materials with Si-based micro-electromechanical systems (MEMS) technologies, to evaluate the impact of the related planar µTEG architecture (dimensions and shape of the active material) and device thermal management (heat dissipator integration with >100x extracted power improvement), and to benchmark their performance. As a proof-of-concept, 6 mol% niobium-doped strontium titanate (Nb:STO) thin films are patterned on square-shaped SiO2/Si3N4 planar membrane de-vices, a heat dissipator is implemented, and the performance of the related µTEG is evaluated.  Nb:STO thin films and integration SrTiO3 (STO)-based thin films offer a large variety of physical properties such as metal-insulator transition, ferro-, piezo-, pyro- and flexo-electricity, high thermopower, ferro-magnetism, superconductivity, high electron mobility at low temperatures and resistive switching [24–27] making STO the “work horse” of many oxide-based devices. It is ACCEPTED MANUSCRIPT  well know that Nb-doping in Ti-site of pristine insulating SrTiO3 (Nb:STO) makes it an n-type conductor, which exhibits good thermoelectric properties [28,29]. The highest power factor (PF = σ·S2) of ≈2.6 mW·m−1·K−2 was achieved near room temperature for STO films which are doped between 5–8% Nb [30,31].  In this work, Nb:STO thin films were grown by Pulsed Laser Deposition (PLD) with the same conditions previously reported in [32]. Structural analysis of the as-grown films was carried out by standard X-ray diffraction in a 2θ/ω configuration using Pana-lytical X′pert pro-MRD diffractometer. The thicknesses of the films were determined by deposition time calibration combined with using physical etching (RIE) and profilome-ter. µTEG Device Architecture The µTEG is a planar device that induces a temperature gradient across the thermoelec-tric material lying on a membrane (Figure 1). A doped silicon (d-Si) platform in the central part of the membrane hosts a metal serpentine that operates as a heater and thermometer, and homogenises the temperature. The serpentine is connected with a 4-wire scheme (force wires: F+ and F-, and sense wires: S+ and S-) to avoid contact re-sistance during resistance measurement. Current collectors contact the thermoelectric material at the edge of the d-Si platform (internal collector) and over the bulk silicon (external collector). The external current collector has two metal tracks that connect at the external contact pads. The chip hosts five devices (D1 to D5) with geometrical vari-ations in the lateral length of the internal platform (w) and in the gap between the plat-form and the bulk Si (g) (Table 1). The architecture of the devices allows the evaluation of the performance of the µTEG in two different modes. In test mode, a thermal gradient is generated across the ACCEPTED MANUSCRIPT  TE material by forcing a controlled current to the serpentine on the d-Si platform, which acts as a heater, and maintaining the bulk Si at room temperature. In harvest mode, the thermal gradient is naturally generated by placing the Printed Circuit Board (PCB) where the chip is mounted on a hotplate. The serpentine on the d-Si platform is used as a thermometer to evaluate the thermal gradient. The current on the thermometer is cho-sen to avoid Joule heating. This harvest mode is closer to an actual application, while the test mode allows evaluating the maximum possible performance under a given thermal gradient. In both cases, the heater can be used as a thermometer once its Tem-perature Coefficient of Resistance (TCR) has been characterized. Fabrication  The micro-fabrication of the µTEG is divided into two blocks. The first block comprises the main process steps to fabricate the platforms. It is performed at a wafer-scale level. The second block focuses on the integration of the thermoelectric Nb:STO thin film into the µTEG, and it is completed at chip-level because of sample size limitations at the PLD system. Within the first block, the Si is selectively doped with boron to concentrations in the order of 1020 at cm-3 to define the d-Si platforms and the contour of the membrane areas. Next, 100 nm SiO2 are thermally grown and 300 nm Si3N4 are deposited by Low Pressure Chemical Vapor Deposition (LPCVD) on both sides of the wafer. This bilayer will form the membrane where the TE oxide material is to be deposited. Then, windows are patterned on the backside of the wafers by optical lithography and RIE, and a partial KOH etching of the Si is performed to leave 150 μm of bulk Si under the platform for structural robustness. At this point, the wafer is diced into chips. ACCEPTED MANUSCRIPT  Within the second block, the Nb:STO thermoelectric layer is first deposited by PLD. The thickness of the Nb:STO thin film layer (tNb:STO) on the chip reported here is 149 nm. Then, the Nb:STO thin film is patterned by optical lithography followed by a dry etching process with Ar plasma. Next, a 200 nm thick SiO2 layer is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) to serve as an interlevel dielec-tric and contacts to the Nb:STO are opened by optical lithography and wet etching. The metal layer is defined by an optical lithography, sputtering of 30 nm of Ti plus 200 nm of W and a lift-off process. Last, the exposed Si on the backside is chemically etched with KOH to release the membranes. (see Fig. S1 with steps detailing fabrication pro-cess). The chip includes a set of electrical test structures (see Fig. S2) to evaluate elec-trical technological parameters like the sheet resistance (Van der Pauw test structures) and the contact resistance between conducting layers (Kelvin test structure). The electri-cal conductivity is calculated based on the sheet resistance measurements and the thick-ness of the layer (σ = 1/(R□∙t)). The sheet resistance obtained for the Nb:STO is R□,Nb:STO = 49 kΩ and the calculated electrical conductivity is σNb:STO = 1.37 Ω-1·cm-1. The con-tact resistance between metal and Nb:STO is Rc = 6.8·10-3 Ω·cm2 on a 20 x 20 µm2 con-tact area (see Table S1). Characterization  Before evaluating the performance of the device in test or harvest modes, the heaters in the centre of each platform need to be calibrated by measuring their temperature coeffi-cient of resistance (TCR) to use them as thermometers. To calculate the thermal gradient seen by the thermoelectric material, the temperature of the bulk Si was measured on ACCEPTED MANUSCRIPT  similar setups. It was determined to be the same temperature as that of the bottom PCB within ±0.5 ºC. TCR measurements were made on a PCB with the wire-bonded device inside an oven. Before any measurement was made, the highest possible current at which the heater temperature remained stable and unaffected by Joule heating was determined. As an additional test, the open circuit output voltage of the device, VOC, was also evaluated at different currents on the heater to validate that they would not generate a temperature gradient. It was found that 50 µA was the highest current that did not generate a meas-urable VOC in any of the devices on the chip. The resistance of the heaters was measured with this current at six different temperatures, ranging from room temperature (RT) to 175 °C. Then, the TCR value for each of the heaters can be obtained using equation (3):  𝑅=𝑅 · 1+𝑇𝐶𝑅 · 𝑇-𝑇  (3) where R0 is the value of the resistance at T = T0, and T0 is the room temperature.  In addition to the thermoelectric characterization, a dedicated chip was used to measure the in-plane thermal conductivity by the 3ω Völklein method [17]. The ob-tained value for a 25 nm thick sample of Nb:STO was kNb:STO = 3.118 W·m-1·K-1 at room temperature. The obtained value is lower than bulk STO due to phonon boundary scattering in thin films and the additional point-defect scattering introduced by Nb dop-ing, Device performance and discussion The device performance was evaluated by applying current to the heater (test mode). Adjusting the current makes it possible to control the temperature of the central part of the membrane, while the temperature of the cold side was measured with a thermocou-ACCEPTED MANUSCRIPT  ple on the bottom of the PCB. For each ΔT across the device, a performance plot (volt-age and power vs. current) was obtained. Figure 2 a-e) shows the performance plots for the five devices on the chip at different ∆T. The maximum power (Pmax) obtained was for the D4 device with a total of 53.26 nW at ∆T = 152 K. The maximum power density (Pdens = Pmax/Area) resulted in 8.32 µW·cm-2. To compare with other devices at different temperature gradients it is useful to report the specific power density as defined in [11] which is Γ = 0.36 nW·cm-2·K-2. From the slope of the I-V curves shown in Figure 2, it is possible to calculate the electrical resistance (R) of the µTEG, which in this case is mainly dominated by the thermoelectric material. Then, plotting the maximum power for each device at different ∆T versus the electrical resistance (see Figure 2f), it be-comes clear the importance of a small electrical resistance in a power generator. The highest output power was obtained for device D4, which has the smallest electrical re-sistance.  From the slope of the VOC vs ΔT curves in Figure 2 we calculated an average Seebeck coefficient of S = -135.7 ± 8.4 µV·K-1 (see Figure S3). The thermal conduct-ance (K) defined as the ratio between the heater power and the temperature gradient obtained, was calculated from the slope of the heater power vs ΔT curve, giving values from 62 to 105 µW·K-1 depending on each device (see Figure S4). Using data from har-vest and test modes, the thermal conductance of the device KTEG can be obtained (see S5 model and discussion). Each device was also measured in harvest mode, by placing the PCB on a hot-plate, with temperatures ranging from 50 to 175 °C. As shown in Figure 3c, the VOC measured in harvest mode was significantly lower than in test mode. This discrepancy is due to the large thermal resistance of the central part of the membrane and the ambi-ent under natural convection conditions. Since thermal resistance is inversely propor-ACCEPTED MANUSCRIPT  tional to the surface area, smaller areas result in greater thermal resistance. For exam-ple, when the device D4 was placed on a hotplate at 175 ºC, the central part of the membrane reached 151 ºC, yielding a temperature gradient of 24 ºC across the TE mate-rial —16% of the total gradient between the hotplate and room temperature. This ther-mal bottleneck is irrelevant in test mode, where the platform temperature is directly con-trolled via a heater (see Figure S5 and discussion).  Optimizing thermoelectric harvesting devices requires a multiscale design ap-proach—enhancing not only material properties but also device architecture and system-level thermal management. To improve the performance of the µTEG, a heat dissipator was mounted on top of the chip, as shown in Figure 3a and 3b. For effective operation, the dissipator must contact only the central regions of the membranes, thereby minimiz-ing thermal resistance to the ambient. To achieve this selective contact, we designed and micromachined custom Si adapters that support the dissipator while minimizing thermal coupling with the hot regions of the device. A similar strategy was previously reported in reference [21]. These adapters consisted of 300 µm thick Si square plates with a smaller lateral dimension than the chip, each equipped with 5 pillars located on top of each of the central membranes. Additionally, four corner pillars 200 µm thick, that act as spacers, were included to support the weight of the dissipator and prevent any dam-age to the membranes. The dissipator resulted in a 61-fold increase in power output compared to the setup without this thermal management element (Pmax = 0.07 nW vs Pmax = 4.28 nW for THP = 175 ºC), as shown in Figure 3c-d). The power output increase reached a factor ca. 110 with the dissipator and under forced air (1.7 m·s-1) convection (Pmax = 7.75 nW for THP = 175 ºC, see Figure 3e). While thermal management with a dissipator and forced convection provided better results, the power generated in harvest mode using this de-ACCEPTED MANUSCRIPT  vice architecture still remains approximately seven times lower than in test mode, high-lighting the importance of thermal management at device level. A finite element model has been developed to identify possible improvements and compare with experimental results. Figure 4 shows two cases: a) the µTEG under natural convection; and b) the µTEG with adapter and dissipator under a forced convection corresponding to air at 1.7m·s-1. The heat exchange coefficient, which defines how much heat is exchanged with the ambient, is set at h = 10 W·m-2·K-1 for the natural convection case and h = 20 W·m-2·K-1 for the forced convection case. The adapter and dissipator are hidden in the left image of b) to compare the temperature map for both configurations. Both models have a Dirichlet boundary condition applied at the bottom of the µTEG corresponding to the hotplate temperature and set at THP = 100 ºC, and the air temperature surrounding the device is set at Tamb = 25 ºC. A thin layer of thermal paste has been added on the contact surfaces between the adapter and the µTEG (the four corners and five membranes) with a thickness of 10μm and a thermal conductivity of 3 W·m-1·K-1 (no pressure is applied in the adapter and dissipator assembly, to minimize the risk of membrane collapse). The maximum power obtained for the D4 device in the model is Pmax = 5.29pW for the the µTEG alone, and Pmax = 360.36pW for the µTEG with adapter and dissipator, resulting in a 68-fold improvement. While the match with experimental results is not quantitative, a similar improvement is obtained when comparing both thermal management options. The main inaccuracies of the model are the convection boundary conditions and the thermal contact between adapter and µTEG. In addition, it has been identified that some parasitic heat-flow paths form the four corner pillars reach the membrane, reducing its performance. Efforts are now being taken to modify the adapter design, especially the ACCEPTED MANUSCRIPT  corner pillars (combining low thermally conducting ceramic materials with silicon microfabricated parts, and reducing the footprint) to enhance the power output.  Combining the different results obtained from electrical conductivity (σNb:STO = 1.37 Ω-1·cm-1), thermal conductivity (κNb:STO= 3.118 W·m-1·K-1) and average Seebeck coefficient (SNb:STO = -135.7 µV·K-1), we can compute the material power factor and zT, resulting in PF = 2.52 µW·m-1·K-2 and zT = 2.43·10-4 at T = 300 K. Similar calculations can be done for the device ZT. In this case, if we focus on the best performing device (D4), we need the electrical conductance (GD4 = 1/RD4 = 3.23·10-4 Ω-1), the thermal conductance (KTEG,D4 = 79.37 µW·K-1, see S5) and the Seebeck coefficient (SD4 = -143.2 µV·K-1, see Fig S3). The calculated value for T = 300 K is ZT = 2.50·10-5. These results are significantly lower than the state-of-the-art values reported for Nb:STO. While both the thermal conductivity and Seebeck coefficient are consistent with previously reported values, the electrical conductivity measured in our device (as listed in Table 1) is sub-stantially lower than the values reported in the literature for 6% Nb-doped STO [31,33]. This discrepancy may be attributed to the fact that most reported values for Nb:STO are obtained from films grown on lanthanum strontium aluminium tantalate (LSAT) sub-strates and other crystalline substrates that promote crystalline and epitaxial growth. In contrast, in our case, Nb:STO was deposited onto an amorphous substrate, namely LPCVD-SiNx, resulting in a non-epitaxial and polycrystalline film. Consequently, its functional properties are degraded due to the distinct microstructural characteristics in-duced by growth on an amorphous substrate, as opposed to those achieved on substrates optimized for epitaxy and crystallinity. With the integration of appropriate buffer layers (like TiO2 [34–36] or CeO2 [37,38]), the electrical conductivity of our TE thin film could potentially match the reported value of 800 S·cm-1 [32]— corresponding to a 149 nm-thick 6% Nb:STO layer at 300 K. Based on our measured Seebeck coefficient and ACCEPTED MANUSCRIPT  thermal resistance, this would translate into a power factor of S2·σ = 1.47 mW·m-1·K-2, yielding a zT = 0.142 and ZT = 1.46·10-2 at 300 K.  A final comparison with state-of-the art references has been included in Table 2 for the most relevant parameters in terms of µTEG performance. Data from our D4 de-vice are also included for comparison, and a D4* device where the electrical conductivi-ty could reach the 800 S·cm-1 value. The table shows the relevance of the internal re-sistance which has a huge impact on the final Pmax obtained, as well as the impact of a proper architecture which facilitates the heat extraction in microstructures reflected in the final ΔT seen by the thermoelectric material. Conclusions Most efforts in the thermoelectric community are focused on optimizing the material zT, and very few are dedicated to thermal management at device (architecture) and system level to improve ZT. In contrast, this work focuses on developing a versatile test plat-form to evaluate almost any thermoelectric material in thin film form under real operat-ing conditions. While the obtained results do not show an alternative to state-of-the-art thermoelectric devices, they prove the platform flexibility to evaluate the integration of thin film Nb:STO and to evaluate its performance as a µTEG. To the authors knowledge, this work is the first reporting a thin film Nb:STO based µTEG. Acknowledgements The research leading to these results has received funding from the European Union’s H2020 Programme under Grant Agreement no 824072 – HARVESTORE. Also sup-ported by the project ThinTEG (PID2022-142003OB-C22) financed by MCIN/AEI/10.13039/501100011033/FEDER, UE, by the European Social Fund Plus (ESF+) through grants RYC2022-038370-I and RYC2022-037016-I, and by CEX2023-ACCEPTED MANUSCRIPT  001397-M, financed by MICIU/AEI/10.13039/501100011033. This work acknowledges the financial support from the Agència de Gestió d’Ajuts Universitaris i de Recerca (AGAUR) of the Generalitat de Catalunya (2021 SGR 00497). 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D1 D2 D3 D4 D5 w [µm] 400 300 400 400 500 g [µm] 400 400 600 200 400 Area = (w+2g)2 [mm2] 1.44 1.21 2.56 0.64 1.69   ACCEPTED MANUSCRIPT   Figure 1: a) Schematic cross section of the µTEG device corresponding to A-A’ in b). b) Optical top view microscope image of a single device (D4). c) Picture of the 1.5x1.5 cm2 chip mounted on a PCB for thermoelectric characterisation (top) and optical micro-scope image of a wire-bonded chip showing the five different devices (bottom).   ACCEPTED MANUSCRIPT    Figure 2. a-e) test mode performance plots for the five devices exposed (D1 to D5) to different ∆T. f) Influence of electric resistance on the maximum power generated by the five devices at different ∆T. All ∆T reported are relative to room temperature Tamb=25ºC.    ACCEPTED MANUSCRIPT    Figure 3: a) Scheme of the dissipator mounting strategy by using an intermediate adapt-er for harvest mode measurements and placing the PCB on top of a hotplate. b) Image of the PCB containing the chip with adapter and dissipator on top. Performance plots in harvest mode for the device D4 with different thermal management configurations, with hot-plate temperatures from 50 °C to 175 °C, under c) natural convection, d) natural convection with dissipator, and e) forced convection with dissipator.    ACCEPTED MANUSCRIPT   Figure 4: Temperature (in ºC) results of the finite element model (COMSOL) corresponding to a) the µTEG in natural convection with heat exchange coefficient h = 10 W·m-2·K-1 and b) the µTEG with adapter and heat dissipator under forced convection with h = 20 W·m-2·K-1, corresponding to an air velocity of 1.7m·s-1. A temperature of THP = 100 ºC is set at the bottom of the model to account for the hotplate temperature and Tamb = 25ºC.    ACCEPTED MANUSCRIPT  Table 2. Comparison with state-of-the-art references with D4 device for most relevant parameters for µTEG performance. Where available, ZT and zT are evaluated at 300K. All values found in the references are in bold, while those in italics are calculated from data in the references. D4* corresponds to the D4 device assuming an electrical conductivity of 800 S·cm-1 instead of the obtained one of 1.37 S·cm-1. Ref Γ μW·cm-2·K-2 Pdens μW·cm-2 Rint Ω zT/ZT footprint cm2 ∆T (condi-tion) K [11] 0.052 1.3 52.8e6 -/- 1 5 (forced) [21] 6.4e-3 67.45 51.04 -/- 0.49 49.5 (THP=200ºC) [22] 1.3 100 38.8 0.02/0.016 0.077 10 (RT+10ºC) D4 3.6e-4 1.21 3096 2.4e-4/2.5e-5 6.4e-3 46.1 (THP=175ºC) D4* 0.21 707.1 5.302 0.142/0.0146 6.4e-3 46.1 (THP=175ºC)    ACCEPTED MANUSCRIPT    GraphicalAbstract1   ACCEPTED MANUSCRIPT  Supplementary Information A novel approach to micro-fabricated thermoelectric generators with SrTiO3 Joaquin Santandera, Iñigo Martin-Fernandeza, Carlos Carbonella, Alex Ro-dríguez-Iglesiasa, Laura Fuentes-Rodrígueza, Marta Fernández-Regúleza, Llibertat Abada, Aitor F. Lopeandiab,c, Arindom Chatterjeed, Nini Prydsd, Luis Fonsecaa, and Marc Sallerasa* aInstitute of Microelectronics of Barcelona (IMB-CNM-CSIC), 08193 Bellaterra, Spain. bPhysics Department, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain. cGTNAM at Institut Català de Nanociència i Nanotecnologia (ICN2), 08193 Bellaterra, Spain. dDepartment of Energy Conversion and Storage, Technical University of Denmark, 2800 Kgs Lyngby, Denmark. *marc.salleras@csic.es  ACCEPTED MANUSCRIPT   Figure S1: Schematics of the fabrication scheme. The fabrication is divided in 2 blocks. Block 1 comprises the process steps at a wafer-scale level. Block 2 comprises the pro-cess steps at a chip-scale level. (1) Starting wafers; (2) Selective doping of Si with BBr3; (3) Growth of 100 nm SiO2 by thermal oxidation (4) deposition of low stress Si3N4 by LPCVD; (5) Optical lithography followed by RIE and photoresist removal to pattern the membrane windows; (6) Partial wet etch with KOH of the Si and wafer dic-ing into chips; (7) PLD deposition of the Nb:STO; (8) Optical lithography followed by Ar plasma and photoresist removal to pattern the Nb:STO; (9) PECVD deposition of 200 nm SiO2 as interlevel oxide; (10) Optical lithography, wet etching, and photoresist removal to define the bias to the Nb:STO; (11) Optical lithography, evaporation of 10 nm Ti and 200 nm W and lift-off to pattern the current collectors and the heaters, the tracks and the metal pads; and (12) Complete KOH etching of the Si to define the mem-branes.   ACCEPTED MANUSCRIPT   Figure S2. Test structures used for the measurement of electrical parameters. The chips include a set of electrical test structures able to measure basic electrical tech-nological parameters like the sheet resistance of conducting layers (Van der Pauw test structures, lower left image in Figure S2) and the contact resistance between conducting layers (Kelvin test structure, lower right image in Figure S2). Table S1 summarizes the obtained values, which confirm that the chips were fabricated as expected. The value of the sheet resistance of the Nb:STO permits the calculation of the electrical conductance provided the thickness of the layer (149 nm).   ACCEPTED MANUSCRIPT  Table S1. Measurements obtained for the technological parameters: sheet resistances of the metal and of the Nb:STO layers and contact resistance between the metal and the Nb:STO layers in a 20 x 20 µm2 contact area. R□ metal 1.3 Ω/□ R□ Nb:STO 49 kΩ/□ Rc metal to Nb:STO 1.7 kΩ  ACCEPTED MANUSCRIPT   Figure S3. Determination of the Seebeck coefficient (S) for each of the five devices from the slope of the VOC vs ΔT curves. The average is S = -135.7 ± 8.4 μV·K-1.   ACCEPTED MANUSCRIPT   Figure S4. Determination of the thermal conductance (K) of the five devices from the slope of the ΔT vs heater power curves.   ACCEPTED MANUSCRIPT   Figure S5: Simplified thermal model of the µTEG. In the calculation of the thermal conductance of the TEG (KTEG) the simple thermal model in Figure S5 is used. In this model the node Tcold is where the heater/thermometer is placed and Thot is the hotplate. KTEG is the thermal conductance of the device (the thermoelectric membrane), KLK is the leakage thermal conductance (through parasitic heat-flow paths), and KS is the thermal conductance from the heater/thermometer to-wards the ambient. For this discussion, we will focus on D4 device and will ignore the KLK term as it is ex-pected to be much smaller than KTEG. From our test mode results, we can calculate the thermal conductance from the slope of ΔT vs heater power curves (Figure S4) resulting in KD4 = 94.48·μW·K-1. According to the thermal model, this thermal conductance cor-responds to the parallel connection of KTEG and KS, therefore KD4 = KTEG,D4 + KS,D4. In harvest mode we set the hotplate temperature at 175 ºC, and the heater (used as a ther-mometer) measures a temperature of 151 ºC, while the ambient temperature measured is 25 ºC. Then we can calculate for D4: 𝑄=𝑑𝑇 · 𝐾 → 𝑄= 175-151 ℃ · 𝐾 = 151-25  ℃ · 𝐾  24  ℃ · 𝐾 = 126  ℃ · 𝐾 → 𝐾 = 126 24⁄ · 𝐾 = 5.25 · 𝐾   And using:    𝐾 +𝐾 =94.48 ·  μ𝑊 · 𝐾  We can obtain:   𝐾 =79.37 · μ𝑊 · 𝐾 → 𝐾 =15.12 · μ𝑊 · 𝐾  ACCEPTED MANUSCRIPT  The KTEG value obtained can be used to calculate a ZT value.   ACCEPTED MANUSCRIPT