# Fileset

[Supporting infomation_240614_ACS_Appl_Mater_Interface.docx](https://mdr.nims.go.jp/filesets/b2812016-bfba-4501-b469-57867a5a0616/download)

## Creator

[Yoshitaka Shingaya](https://orcid.org/0000-0002-5926-3302), [Takuya Iwasaki](https://orcid.org/0000-0002-1103-2433), [Ryoma Hayakawa](https://orcid.org/0000-0002-1442-8230), Shu Nakaharai, [Kenji Watanabe](https://orcid.org/0000-0003-3701-8119), [Takashi Taniguchi](https://orcid.org/0000-0002-1467-3105), [Junko Aimi](https://orcid.org/0000-0003-1339-0581), [Yutaka Wakayama](https://orcid.org/0000-0002-0801-8884)

## Rights

This document is the Accepted Manuscript version of a Published Work that appeared in final form in ACS Applied Materials & Interfaces, copyright © 2024 American Chemical Society after peer review and technical editing by the publisher. To access the final edited and published work see https://doi.org/10.1021/acsami.4c06116[In Copyright](http://rightsstatements.org/vocab/InC/1.0/)

## Other metadata

[Multifunctional in-memory logics based on a dual-gate antiambipolar transistor toward non-von Neumann computing architecture](https://mdr.nims.go.jp/datasets/a8d5fe00-0598-40e9-b93e-2289f7d3c18d)

## Fulltext

Supporting informationMultifunctional in-memory logics based on a dual-gate antiambipolar transistor toward non-von Neumann computing architectureYoshitaka Shingaya†, Takuya Iwasaki†, Ryoma Hayakawa†*, Shu Nakaharai†, Kenji Watanabe‡, Takashi Taniguchi†, Junko Aimi§*, Yutaka Wakayama†*†Research Center for Materials Nanoarchitectonics (MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan‡Research Center for Functional Materials, National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan§Research Center for Macromolecules and Biomaterials, National Institute for Materials Science (NIMS), 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047, Japan*Email: HAYAKAWA.Ryoma@nims.go.jp, AIMI.Junko@nims.go.jp, WAKAYAMA.Yutaka@nims.go.jp1. Reconfigurable two-input logic circuits using non-volatile memory functionsWe demonstrated the electrical switching of two-input logic circuits by using the non-volatile memory effect of the polystyrene with a zinc phthalocyanine core (ZnPc-PS4). Figures S1a-S1d show four examples of the electrical switching of the two-input logic circuits, namely NAND/NOR, XOR/NAND, OR/NAND, and OR/XOR circuits. In all the circuits, the top-gate voltage (Vtg) and the bottom-gate voltage (Vbg) were employed as input signals 1 and 2, respectively. The output signal, “1” or “0”, is defined by whether |Id| is below or above 2.5 nA. Figure S1a shows the electrical conversion between the NAND and the NOR circuits. In the initial state, the low logic state “0” was output at (Vtg, Vbg) = (“1”, “1”). In contrast, Iout exhibited the high logic state “1” for the other input signal combination. This operation corresponds to the NAND circuit. Then, a 10 times-negative Vtg pulse (Vtg = −15 V, Pwidth = 10 s) induced conversion from the NAND to the NOR circuit. Id represented the high logic state “1” only when (Vtg, Vbg) were equal to (“0”, “0”), which is the same as that of the NOR circuit. Consequently, the NOR circuit was restored to a NAND circuit by applying a 10-times positive Vtg pulse (Vtg = 15 V, Pwidth = 10 s). Importantly, the reconfiguration of the NAND and NOR circuits was realized without changing the input signals. In this manner, Fig. S1b-S1d show the electrical transitions between XOR and NAND, OR and NAND, and OR and XOR.Figure S1. Reconfigurable two-input logic circuits: (a) NAND/ NOR, (b) XOR/NAND, (c) OR/NAND, and (d) OR/XOR.2. AFM observation of the fabricated deviceAtomic force microscope (AFM) observations were conducted to measure the thicknesses of the WSe2, ReS2 and h-BN layers (Figures S2a-c). Figure S2a shows an AFM image of the bottom-gate AAT before forming the top-gate configuration. The thicknesses of WSe2 and ReS2 were estimated to be 13 nm and 11 nm, respectively. The thickness of the bottom h-BN gate insulator was determined as 24 nm. Furthermore, the thickness of the top h-BN gate insulator was decided at 33 nm from the AFM image shown in Figure S2c.Figure S2. AFM images of (a) WSe2 and ReS2 channel layers, (b) bottom and (c) top h-BN gate insulators3. Switching property of the dual-gate AAT with ZnPc-PS4 nano-floating gateFigure S3a shows the transfer characteristics of the dual-gate AAT with the ZnPc-PS4 nano-floating gate after applying alternating negative Vtg pulses (Vtg = −15V, Pwidth = 10 s, 5 times) and positive Vtg pulses (Vtg = 15V, Pwidth = 10 s, 5 times). The variations in Vpeak and Ipeak, which are extracted from Figure S3a, are plotted as a function of the number of switching cycles in Figure S3b. The Vpeak and Ipeak values were almost constant after the repeated switching processes. Figure S3. (a) Switching property of dual-gate AAT with nano-floating gate. (b) Variation of Vpeak and Ipeak values as a function of the number of switching cycles.4. Retention property of the ZnPc-PS4 nano-floating gateThe retention property of the carrier-trapping states in the ZnPc-PS4 nano-floating gate was examined in ReS2 (Figure S4a) and WSe2 transistors (Figure S4b). The black lines in both figures show the variations of the drain currents in the initial states. In the ReS2 transistor (Figure S4a), the hole-trapping state (blue line) after applying a negative Vtg pulse and the electron-trapping state (red line) after applying a positive Vtg pulse were maintained for at least 2000 s. The WSe2 transistor also indicated a retention time of at least 2000 s for the hole trapping state (blue line in Figure S4b). Conversely, the trapped electrons in the ZnPc-PS4 layer were immediately released in the WSe2 transistor as indicated by the red line in Figure S4b.Figure S4. Retention properties of the ZnPc-PS4 nano-floating gate in (a) ReS2 and (b) WSe2 transistors.1image4.pngimage1.jpegimage2.pngimage3.png