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[Masahiro Hara](https://orcid.org/0000-0001-9748-8011), [Toshihide Nabatame](https://orcid.org/0000-0002-5973-0230), [Yoshihiro Irokawa](https://orcid.org/0000-0002-6531-4356), Tomomi Sawada, Manami Miyamoto, Hiromi Miura, Tsunenobu Kimoto, Yasuo Koide

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[A three-step surface treatment and its impacts on electrical properties of c- and m-face GaN/Al2O3 MOS structures](https://mdr.nims.go.jp/datasets/94e92e56-e296-4f09-b92d-d93a0866662c)

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A three-step surface treatment and its impacts on electrical properties of c - and m -face GaN/Al2O3 MOS structuresAaMMabAKGMTIR1mrttfvp(dwoqtiif1uhRMaterials Science in Semiconductor Processing 196 (2025) 109606 A1 Contents lists available at ScienceDirectMaterials Science in Semiconductor Processingjournal homepage: www.elsevier.com/locate/mssp   three-step surface treatment and its impacts on electrical properties of c- nd m-face GaN/Al2O3 MOS structuresasahiro Hara a,b ,∗, Toshihide Nabatame b, Yoshihiro Irokawa b, Tomomi Sawada b, anami Miyamoto b, Hiromi Miura b, Tsunenobu Kimoto a, Yasuo Koide bDepartment of Electronic Science and Engineering, Kyoto University, Nishikyo, Kyoto, 615-8510, JapanNational Institute for Materials Science, Tsukuba, Ibaraki, 305-0044, Japan R T I C L E  I N F Oeywords:aNOSFETsrench sidewallnterface trapseliability A B S T R A C TIn this study, a three-step surface treatment, composed of SiO2 deposition, subsequent annealing, and SiO2removal, is adopted for the fabrication of c- and m-plane n-type GaN/Al2O3 MOS structures, and the impact of the proposed process on electrical properties and its crystal face dependence are systematically investigated. While no significant changes are observed after the proposed surface treatment for m-face GaN, an identical process causes changes in the properties of c-face GaN MOS structures: an about 0.2V lower flat-band voltage (V FB) and an about 0.2 eV higher conduction band offset, associated with a change in the thickness or crystalline quality of a gallium oxide (GaO𝑥) layer on the c-face GaN surface. The modified energy band alignment leads to a reduced gate leakage current, reducing the V FB drift after high-field positive bias stress (4.5MV∕cm) almost by half only for c-face GaN MOS structures. The fact that even an identical process has a crystal face-dependent impact on the properties of GaN MOS structures is important in developing the fabrication process of GaN planar and trench MOSFETs.. IntroductionGallium nitride (GaN) is an attractive wide-bandgap semiconductor aterial that can improve the trade-off relationship between on-state esistance and blocking voltage in power devices [1–4], mainly thanks o its high critical electric field (2.5–3.5MV∕cm) [5–7]. Following he intensive research and development of GaN-based heterostructure ield-effect transistors (HFETs) for high-frequency devices [8,9], GaN ertical metal–oxide–semiconductor FETs (MOSFETs) have become a romising alternative to silicon (Si) insulated gate bipolar transistors IGBTs) and silicon carbide (SiC) MOSFETs as high-voltage switching evices [10,11]. There are two major structures of power MOSFETs, hich are planar and trench structures with a MOS channel formed n c- and m-plane GaN, respectively. Thus, the formation of a high-uality GaN/dielectric interface on c- and m-faces is key to improving he performance and reliability of GaN MOSFETs.In the fabrication of GaN MOS structures, aluminum-based gate nsulators, such as aluminum oxide (Al2O3) [12–16], aluminum sil-cate (AlSiO) [17,18], aluminum oxynitride (AlON) [19,20], and so orth, have been widely adopted. A low interface state density (𝐷it ∼011 cm−2eV−1) near the conduction band edge (𝐸C) has been reported sing n-type GaN MOS structures [21–23]. Reflecting a low 𝐷it near ∗ Corresponding author at: Department of Electronic Science and Engineering, Kyoto University, Nishikyo, Kyoto, 615-8510, Japan.E-mail address: hara@semicon.kuee.kyoto-u.ac.jp (M. Hara).𝐸C, besides, a very high channel mobility exceeding 100 cm2V−1s−1 has been demonstrated [24,25], making the GaN MOS structures with an aluminum-based gate dielectric promising for high-performance power MOSFETs.On the other hand, the long-term reliability of the MOS structure is still a concern. Few reports have performed stress tests and investigated charge-trapping behavior for aluminum-based gate insulators [26–28]. For example, it was indicated for a GaN/AlSiO system that the flat-band voltage (𝑉FB) drift after applying positive-bias stress (PBS) reaches over 1.5V in 300 s unless the temperature of post-deposition annealing (PDA) is optimized. Hence, it is crucial to establish a formation process of GaN MOS structures that does not cause any degradation of electrical properties during device operation.To improve the reliability of GaN MOS structures, we have focused on surface treatment before the gate dielectric formation. According to previous studies, the 𝐷it value of c- and m-face at GaN/Al2O3 MOS interfaces is effectively reduced by post-metallization annealing (PMA) even at a low temperature (300 ◦C) [21,23], indicating that the surface of GaN and/or the native oxide layer [29,30] is inherently unstable. In this sense, we recently proposed a three-step surface treatment, named the dummy SiO2 process [31]. In this method, (1) deposition of silicon ttps://doi.org/10.1016/j.mssp.2025.109606eceived 16 December 2024; Received in revised form 27 March 2025; Accepted 2vailable online 7 May 2025 369-8001/© 2025 The Authors. Published by Elsevier Ltd. This is an open access ar0 April 2025ticle under the CC BY license ( http://creativecommons.org/licenses/by/4.0/ ). https://www.elsevier.com/locate/mssphttps://www.elsevier.com/locate/mssphttps://orcid.org/0000-0001-9748-8011mailto:hara@semicon.kuee.kyoto-u.ac.jphttps://doi.org/10.1016/j.mssp.2025.109606https://doi.org/10.1016/j.mssp.2025.109606http://creativecommons.org/licenses/by/4.0/M. Hara et al. Materials Science in Semiconductor Processing 196 (2025) 109606 Fig. 1. Flow for fabricating c- and m-face GaN/Al2O3 MOS capacitors with and without the dummy SiO2 process.Fig. 2. (a) Typical 𝐶–𝑉  characteristics and (b) flat-band voltage of c- and m-face GaN/Al2O3 MOS structures. The dummy SiO2 process caused a negative shift of 𝐶–𝑉  curves and flat-band voltage only for the c-face samples.dioxide (SiO2) film, (2) subsequent PDA in nitrogen (N2) ambient, and (3) SiO2 removal with buffered hydrofluoric acid (BHF) are performed prior to the gate dielectric formation. Our previous work adopted this process for the fabrication of c-face GaN/Al2O3 MOS structures with the PDA temperature of 800 ◦C and investigated the 𝑉FB stability against PBS [31]. As a result, the proposed process effectively suppressed the 𝑉FB drift during PBS even under a relatively high oxide field of 4MV∕cm. On the other hand, it is still unclear what role the dummy SiO2 process plays in improving the 𝑉FB stability. To elucidate the critical factor contributing to the improved reliability of MOS structures and further develop the proposed process, more detailed investigations of the MOS interface properties are necessary by varying the process condition, such as the temperature of PDA on dummy SiO2. Besides, it is beneficial to clarify the impact of this process on m-face GaN 2 MOS structures, aiming at high-performance and highly reliable GaN trench MOSFETs. In the present study, we fabricated c- and m-face GaN/Al2O3 MOS capacitors with various PDA temperatures on dummy SiO2 and systematically investigated the electrical properties and the surface chemical bonding, discussing their dependency on the crystal face of GaN.2. ExperimentFig.  1 shows the fabrication process of the GaN/Al2O3 MOS struc-tures. The c-face GaN MOS capacitors were prepared with n-type GaN epitaxial layers (donor density: ∼ 2 × 1016 cm−3) grown on n-type GaN(0001) freestanding substrates, while n-GaN epitaxial layers (donor density: 7–8 × 1015 cm−3) on GaN(1010) substrates were used M. Hara et al. Materials Science in Semiconductor Processing 196 (2025) 109606 Fig. 3. Bidirectional 𝐶–𝑉  characteristics of (a) c- and (b) m-face GaN/Al2O3 MOS structures. Hysteresis of 𝐶–𝑉  curve determined using 𝑉FB as a function of the maximum electric field in (c) c- and (d) m-face GaN/Al2O3 MOS structures. The dummy SiO2 process reduced the hysteresis under a high electric field only for the c-face samples.as m-plane samples. The substrates were first cleaned with sulfuric peroxide mixture (SPM) for 5min and BHF for 30 s. For the dummy SiO2 process, a 5 nm-thick SiO2 was deposited on some samples by plasma-enhanced atomic layer deposition (PE-ALD) at the substrate temperature of 300 ◦C with tris(dimethylamino)silane as a precursor. PDA was then performed at various temperatures (600–900 ◦C) in N2ambient for 5min, followed by the SiO2 removal with BHF solution (30 s). Note that the etching rate of 𝛽-gallium oxide with BHF was very low (1.4–2.2 nm∕h), barely etching a gallium oxide layer that would be formed on the GaN surface [31]. Gate dielectric was formed by depositing a 10 nm-thick Al2O3 film by PE-ALD at 300 ◦C with a precursor and oxidant gas of trimethylaluminum and H2O, respectively. A circular-shaped gate electrode with a diameter of about 100 μm was formed on Al2O3 by electron-beam evaporation of Pt, and then, Ti/Pt electrode stack was deposited on the substrate as backside ohmic contacts. Finally, PMA was conducted at 300 ◦C in N2 ambient for 5min. Hereafter, the samples treated with the dummy SiO2 process are labeled with the crystal face and PDA temperature (e.g., c-900 and m-900), while non-treated ones are indicated as c-wo and m-wo for the c- andm-plane samples, respectively.Capacitance–voltage (𝐶–𝑉 ) characteristics of the MOS capacitors were acquired at room temperature with the probe frequency of 1MHzby sweeping the voltage from depletion to accumulation (D to A), and then back to depletion (A to D). Current–voltage (𝐼–𝑉 ) measurements were performed as well. Besides, PBS tests were conducted at room temperature for 300 s in total by systematically varying the stress field from 2.0 to 4.5MV∕cm. After the stress time (𝑡) of 1, 10, 50, 100, 150, 200, 250, and 300 s, 𝐶–𝑉  characteristics were repeatedly measured, and the 𝑉  drift caused by PBS was characterized. The direction of voltage FB3 Fig. 4. Current density–oxide field characteristics of c- and m-face GaN/Al2O3 MOS structures. The dummy SiO2 process made the conduction band offset (𝜙ox) about 0.2 eVhigher only for c-face GaN.M. Hara et al. Materials Science in Semiconductor Processing 196 (2025) 109606 Fig. 5. Flat-band voltage drift versus stress time under various electric field conditions in c-face GaN/Al2O3 MOS structures fabricated without surface treatment (c-wo). The inset shows an example of the 𝐶–𝑉  curve drift under a stress field of 4.0MV∕cm.sweeping for 𝐶–𝑉  measurements after PBS was from accumulation to depletion to avoid electron emission from a trap. Additionally, X-ray photoelectron spectroscopy (XPS) measurements with monochromated Al K𝛼 X-ray (ℎ𝜈 = 1486.6 eV) were performed on the GaN surface before and after the surface treatment, and Ga 3d spectra were compared between different crystal faces. Note that the PDA temperature in the sample preparation for XPS measurement was 800 ◦C, which is the same PDA condition as the literature [31].3. ResultsFig.  2 shows (a) the typical 𝐶–𝑉  characteristics of the GaN/Al2O3MOS capacitors and (b) 𝑉FB versus process condition. Note that 𝑉FBwas determined at a voltage where the capacitance value measured at a high frequency (1MHz) is equal to 𝐶FB = 𝐶ox𝐶s,FB∕(𝐶ox + 𝐶s,FB), where 𝐶ox is the oxide capacitance and 𝐶s,FB is expressed as 𝜀s𝜀0∕𝐿Dusing the dielectric constant of GaN (𝜀s = 10.4𝜀0 and 9.5𝜀0 for c- andm-face, respectively [32]) and the Debye length (𝐿D) [33]. As for thec-face GaN MOS capacitors, 𝐶–𝑉  curves shifted toward a lower voltage side by the dummy SiO2 process, and the 𝑉FB shift was 0.2–0.3V, as plotted in Fig.  2(b). On the other hand, no significant change in 𝐶–𝑉  characteristics and 𝑉FB was observed for the m-face samples. Note that there was only a slight PDA temperature dependence of the 𝐶–𝑉characteristics and 𝑉FB values.Fig.  3 shows the bidirectional 𝐶–𝑉  curves in (a) c- and (b) m-face GaN MOS capacitors, varying the maximum value of the sweeping volt-age (i.e., maximum electric field). The hysteresis of 𝐶–𝑉  characteristics determined by extracting 𝑉FB is plotted against the maximum electric field in Figs.  3(c) and (d). While larger hysteresis was observed with increasing the maximum field, the hysteresis was below 100mV in all the samples. The hysteresis under a higher electric field was reduced by almost half only in the c-plane GaN MOS capacitors, while almost no change in the hysteresis was observed for m-face.The crystal face-dependent impact of the dummy SiO2 process was also found in 𝐼–𝑉  characteristics. Fig.  4 shows the current density through the gate dielectric (𝐽g) as a function of the oxide field (𝐸ox), which is defined as 𝐸ox = (𝑉 − 𝑉FB)∕𝑡ox, where 𝑡ox is the thickness of Al2O3. The gate current measured under a given 𝐸ox was reduced by adopting the dummy SiO2 process only for the c-face samples, while was not affected by the same process for m-face. To determine the conduction band offset (𝜙ox) at the GaN/Al2O3 interface, Fowler-Nordheim (FN) tunneling current was calculated based on the following analytical formula [34,35], 𝐽FN =𝑒3𝐸2ox2exp(−4√2𝑚∗ox 𝜙3∕2ox), (1)16𝜋 ℏ𝜙ox 3𝑒ℏ𝐸ox4 Fig. 6. Flat-band voltage drift versus stress time under the electric field of 2.0 and 4.5MV∕cm in (a) c- and (b) m-face GaN/Al2O3 MOS structures.where 𝑒 is the elementary charge, ℏ is the Dirac constant, and 𝑚∗oxis the effective mass in Al2O3 (0.28𝑚0 [36]). Note that the barrier M. Hara et al. Materials Science in Semiconductor Processing 196 (2025) 109606 Fig. 7. Flat-band voltage drift after 300 s-stress as a function of electric field in (a) c- and (b) m-face GaN/Al2O3 MOS structures.height lowering by the image force effect was considered in the cal-culation [34,35]. The FN tunneling current calculated by varying 𝜙oxis plotted by the dashed lines in Fig.  4. The experimental 𝐽g–𝐸oxcharacteristics for the c-wo and all the m-plane samples were well reproduced with 𝜙ox = 2.30–2.35 eV, while an increased 𝜙ox of 2.50 eVwas obtained for the c-face samples treated by the dummy SiO2 process.In Fig.  5, the 𝑉FB drift caused by PBS with various electric fields is plotted against the stress time for the c-wo sample. 𝐶–𝑉  curves acquired after each stress time with the electric field of 4.0MV∕cm are shown as an example in the inset of Fig.  5. As seen in Fig.  5, a higher stress field led to a larger drift of the 𝐶–𝑉  curves, and the 𝑉FB drift by 300 s-stress with 4.5MV∕cm was as large as 0.8V for the c-wo sample.Then, we compared the 𝑉FB drift by 2.0 or 4.5MV∕cm-stress in thec- and m-face GaN MOS capacitors, as plotted in Fig.  6(a) and (b), respectively. Fig.  7 summarizes the stress field dependence of the 𝑉FBvalues in the (a) c- and (b) m-face samples. As for c-face, the 𝑉FB drift by high-field stress was effectively reduced by the dummy SiO2 process and was 0.4V in the c-900 sample, which was about a half of that in the c-wo sample. In contrast to the improved 𝑉FB stability by the proposed process for the c-face GaN MOS capacitors, almost no changes in the 𝑉FB drift were found in the m-face sample.Fig.  8 shows the Ga 3d core-line spectra of the (a) c- and (b) m-face GaN surfaces treated by the dummy SiO2 process. A fitting analysis with two peaks of Ga-N and Ga-O bonding was performed, and the peak intensity ratio of the two bonding components was characterized, as plotted in Fig.  8(c). Note that the binding energy of Ga-N bonding was 19.6 eV, and the peak value of Ga-O bonding in fitting analysis was given by the energy of 20.4 eV. For c-face GaN, the peak intensity ratio of the surface treated by the dummy SiO2 process was about 1.3 times higher than that of the as BHF-cleaned surface with a native oxide layer, indicating a thicker or denser GaO𝑥 layer on the GaN surface [31]. On the other hand, the peak intensity of Ga-O bonding for the m-face GaN surface was smaller than that of c-face after BHF treatment and was not changed much by the dummy SiO2 process. Thus, it is presumed that an m-face GaN surface has a thin native oxide and is not easily oxidized compared to c-face GaN.4. DiscussionAs presented above, the impact of the dummy SiO2 process is strongly dependent on the crystal face of GaN. Regarding electrical properties, an about 0.2V smaller 𝑉FB and an about 0.2 eV higher 𝜙oxwere found only for the c-face GaN/Al2O3 MOS structures treated with the dummy SiO2 process. Besides, XPS measurements indicated an increase in the thickness or an improved crystalline quality of a surface 5 Fig. 8. Ga 3d spectra of (a) c- and (b) m-face GaN surfaces after BHF cleaning (labeled as w/o) and the dummy SiO2 process. (c) XPS peak intensity of Ga-O bonding normalized by that of Ga-N bonding. A higher peak intensity ratio indicates a thicker or denser GaO𝑥 layer on the surface.GaO𝑥 layer by the proposed process only for c-face GaN. Based on these results, changes in the electrical properties of the c-face GaN/Al2O3MOS structures can be correlated with the structural change of a GaO𝑥layer, that is, a change in the GaO𝑥 layer results in a modified surface energy band structure where the conduction band edge near the GaN surface becomes about 0.2 eV lower.We considered whether the critical factor for the improved 𝑉FBstability against high-field stress observed only in the c-face GaN MOS M. Hara et al. Materials Science in Semiconductor Processing 196 (2025) 109606 Fig. 9. Flat-band voltage drift after 300 s-stress with various electric fields as a function of the total injected charge in c- and m-face GaN/Al2O3 MOS structures. The total injected charge was determined by taking the integral of the current density–stress time characteristics during stress. A higher stress field leads to a larger FN tunneling current and thereby a larger injected charge.structures is not the reduction of oxide traps but the change in the energy band alignment and a reduced FN tunneling current. Thus, we calculated the total injected negative charge by taking the integral of the 𝐽g–𝑡 characteristics during PBS. Fig.  9 shows the relationship between the 𝑉FB drift and the total injected charge after 300 s-stress with various electric fields. Note that the minimum value of the injected charge is about 5 × 10−6 C∕cm2 due to the detection limit of the 𝐼–𝑉measurement. As seen in Fig.  9, the 𝑉FB drift was almost uniquely dependent on the total injected charge, regardless of the crystal face, electric field, and process condition. Therefore, it turned out that the critical role of the dummy SiO2 process is the rearrangement of the energy band alignment of the c-face GaN surface associated with a structural change in the GaO𝑥 layer, improving the 𝑉FB stability in GaN MOS structures. On the other hand, the impact of PDA is not fully understood yet because the 𝑉FB drift after PBS was further reduced at a higher PDA temperature, despite PDA temperature-independent 𝐶–𝑉  and 𝐼–𝑉  characteristics among the c-plane samples. Hence, further investigations, including a two-step treatment without PDA and more detailed structural analyses with various PDA conditions, are required in the future.Since a higher conduction band offset resulting from the formation of a GaO𝑥 interlayer leads to a lower valence band offset, it will also be a subject of future study to investigate the 𝑉FB stability against hole injection by negative bias stress. As for GaN MOS structures, it is reported that a large amount of hole traps exist near the valence band edge [37–40], leading to a significant shift of the threshold voltage and 𝑉FB in GaN MOSFETs by applying a negative gate voltage. While the origin of hole traps is not fully understood even now, several theoretical and experimental studies reported that a GaO𝑥 interlayer is one of the origins of high-density hole traps [41–44]. On the other hand, hole traps at a lower energy level in the gate dielectric will become accessible with the reduced valence band offset by the formation of the GaO𝑥 interlayer, which can also affect the 𝑉FB drift by hole trapping in GaN MOS structures. In this sense, it is important to adopt the proposed process for c- and m-face p-type GaN MOS capacitors (or 6 n-channel planar and trench MOSFETs) and to investigate the hole-trapping behavior and its crystal face dependence, discussing based on the formation of a GaO𝑥 interlayer.5. ConclusionsIn summary, using a proposed surface treatment, named the dummy SiO2 process, the electrical properties and their crystal face dependence of n-type GaN/Al2O3 MOS structures were systematically investigated. While the proposed process was not effective on the properties of m-face GaN MOS structures, the same process made the flat-band voltage smaller by 0.2–0.3V and the conduction band offset higher by 0.2 eV forc-face GaN, resulting from a modified energy band alignment associated with the structural change of a surface GaO𝑥 layer. It was revealed that the energy band rearrangement at the GaN surface (∼ 0.2 eV) and about an order of magnitude smaller FN tunneling current through the gate dielectric are the critical factors of the dummy SiO2 process that contribute to an improved flat-band voltage stability against high-field stress (> 4MV∕cm) in c-face GaN/Al2O3 MOS structures. It was demonstrated that even an identical process can have a different impact on the properties of c- and m-face n-GaN MOS structures, which should be an important insight toward developing the fabrication process of GaN planar and trench MOSFETs.CRediT authorship contribution statementMasahiro Hara: Writing – original draft, Visualization, Validation, Methodology, Investigation, Formal analysis, Data curation. Toshihide Nabatame: Writing – review & editing, Validation, Supervision, Soft-ware, Resources, Project administration, Investigation, Funding acqui-sition, Data curation, Conceptualization. Yoshihiro Irokawa: Writing – review & editing, Validation, Investigation, Formal analysis, Data curation, Conceptualization. Tomomi Sawada: Validation, Investiga-tion, Data curation. Manami Miyamoto: Validation, Investigation, Data curation. Hiromi Miura: Validation, Investigation, Data curation. Tsunenobu Kimoto: Writing – review & editing, Validation, Supervi-sion, Resources, Project administration, Methodology. Yasuo Koide: Writing – review & editing, Validation, Supervision, Resources, Project administration, Funding acquisition.Declaration of competing interestThe authors declare that they have no known competing finan-cial interests or personal relationships that could have appeared to influence the work reported in this paper.AcknowledgmentsThis work was supported in part by the MEXT ‘‘Program for Creation of Innovative Core Technology for Power Electronics’’ (No. JPJ009777).Data availabilityThe data that support the findings of this study are available from the corresponding author upon a reasonable request.References[1] S.J. Pearton, J.C. Zolper, R.J. Shul, F. Ren, J. Appl. Phys. 86 (1) (1999) 1–78.[2] B.J. Baliga, Semicond. Sci. Technol. 28 (7) (2013) 074011.[3] T. Kachi, Japan. J. Appl. Phys. 53 (10) (2014) 100210.[4] F. Roccaforte, P. Fiorenza, G. Greco, R. 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A three-step surface treatment and its impacts on electrical properties of c- and m-face GaN/Al2O3 MOS structures Introduction Experiment Results Discussion Conclusions CRediT authorship contribution statement Declaration of competing interest Acknowledgments Data availability References