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[Yoshihiro Irokawa](https://orcid.org/0000-0002-6531-4356), [Toshihide Nabatame](https://orcid.org/0000-0002-5973-0230), Tomomi Sawada, Manami Miyamoto, Hiromi Miura, [Kazuhito Tsukagoshi](https://orcid.org/0000-0001-9710-2692), [Yasuo Koide](https://orcid.org/0000-0001-8321-9822)

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[Communication—A Powerful Method to Improve Dielectric/GaN Interface Properties: A Dummy SiO<sub>2</sub> Process](https://mdr.nims.go.jp/datasets/15e87626-2621-4167-bd1b-364d5192db12)

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Communication—A Powerful Method to Improve Dielectric/GaN Interface Properties: A Dummy SiO2 ProcessECS Journal of Solid StateScience and Technology     OPEN ACCESSCommunication—A Powerful Method to ImproveDielectric/GaN Interface Properties: A DummySiO2 ProcessTo cite this article: Yoshihiro Irokawa et al 2024 ECS J. Solid State Sci. Technol. 13 085003 View the article online for updates and enhancements.You may also likeInfluence of reactive-ion-etching depth oninterface properties in Al2O3/n-GaN MOSdiodesHirokuni Tokuda, Sayaka Harada, Joel T.Asubar et al.-Prediction of interface and vacancysegregation energies at silver interfaceswithout determining interface structuresRyuken Otani, Shin Kiyohara, KiyouShibata et al.-Understanding interface properties in 2Dheterostructure FETsKosuke Nagashio-This content was downloaded from IP address 144.213.253.16 on 28/08/2024 at 23:12https://doi.org/10.1149/2162-8777/ad6fd2/article/10.7567/1347-4065/ab3d11/article/10.7567/1347-4065/ab3d11/article/10.7567/1347-4065/ab3d11/article/10.7567/1347-4065/ab3d11/article/10.7567/1347-4065/ab3d11/article/10.35848/1882-0786/ab8b6c/article/10.35848/1882-0786/ab8b6c/article/10.35848/1882-0786/ab8b6c/article/10.1088/1361-6641/aba287/article/10.1088/1361-6641/aba287https://pagead2.googlesyndication.com/pcs/click?xai=AKAOjssVRSvPBHA77gT2dn8SL3v0DxbA36gfhjpaxV1_bQssd6raiVLOm3hxmXTmvz_RhuD8JO36w-3e_lIF-opiQqkkC9tmWnicJ9-fN4kYGsswcI4MANU_zaEAcVca7nuosNrOuJ8liNmsZkbVS4axV3vtgXHpCo4OuXJpMtG4dYJW8mYnH8aCrH9jexXKNpe1FqBmUO2YaJzX864z64uuWZEVhTAFxZzvAVKbmK0sugVEC5sYRY961T7oSPu1eaPLvU3BC8iAOb-8B5UNN4xhndzGVmb4wCN4rXyWn0UKRDX6AKQb9rztXyPxPfTFBfFjuaEKnaXeJiy-PuQP95n_iw&sig=Cg0ArKJSzFqwAA599_WM&fbs_aeid=%5Bgw_fbsaeid%5D&adurl=https://www.el-cell.com/products/test-cells/electrochemical-dilatometer/ecd-4-nano/%3Fmtm_campaign%3Diop%2520pdf%2520advert%26mtm_kwd%3Decd-4-nano%26mtm_source%3Dpdf%26mtm_cid%3D2024Communication—A Powerful Method to Improve Dielectric/GaNInterface Properties: A Dummy SiO2 ProcessYoshihiro Irokawa,z Toshihide Nabatame,z Tomomi Sawada, Manami Miyamoto,Hiromi Miura, Kazuhito Tsukagoshi, and Yasuo KoideNational Institute for Materials Science, Tsukuba, Ibaraki 305-0044, JapanWe report a simple and effective method for improving dielectric/GaN interface properties. In the process, a 5 nm thick SiO2 layerwas deposited onto a GaN(0001) substrate via plasma-enhanced atomic layer deposition, followed by annealing at 800 °C for 300 sunder a flowing N2 atmosphere. The SiO2 layer was then removed using buffered HF solution, and Pt/Al2O3/GaN metal-oxide-semiconductor capacitors were fabricated on the substrate. Positive-bias stress tests revealed that the flat-band voltage shifts weresubstantially reduced for devices fabricated using this process, probably because of improved interface crystallinity. This methodcan also be applied to other dielectric/GaN systems.© 2024 The Author(s). Published on behalf of The Electrochemical Society by IOP Publishing Limited. This is an open accessarticle distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2162-8777/ad6fd2]Manuscript submitted July 12, 2024; revised manuscript received July 25, 2024. Published August 28, 2024.With the goal of efficient energy utilization, power devices basedon a wide variety of semiconductor materials have been investigated.GaN is one of the most promising semiconductor materials becauseof its wide bandgap (3.4 eV) and well-developed device fabricationprocesses.1–4 Metal-oxide-semiconductor field-effect transistors(MOSFETs) are a key component in such power devices; therefore,dielectric/GaN interfaces have been intensively studied since the late1990s.5 Among dielectrics, SiO2/GaN has been the mainstream insuch research because of its excellent interface properties.6 As earlyas the 2000s, post-deposition annealing (PDA) was found to reducethe interface state density (Dit) to the lower 1011 cm−2 eV−1 range.7,8In-depth research has revealed that gallium oxide (GaOx) interfacelayers formed at the SiO2/GaN interfaces play a critical role in theoutstanding interface properties;9–14 however, the precise me-chanism for the Dit reduction remains unclear. We have previouslyreported that the GaOx interface layer exhibits a crystallinestructure15,16 that might be related to the lower Dit. In addition,some institutes, including ours, have reported that even the nativeoxide layers on GaN are crystalline rather than amorphous.17–19 Thisfinding is consistent with the difficulty associated with removing thenative oxide layers on GaN.20 Meanwhile, we have also found thatthe native oxide layers on GaN might be defective.18 Thus, defectivenative oxide layers on GaN, which remain even after the cleaningprocess, can adversely affect the dielectric/GaN interface properties.We therefore speculate that PDA reduces the Dit for SiO2/GaN viathe following mechanism: PDA of SiO2/GaN induces oxygendiffusion from SiO2 toward the native oxide layer (i.e., the GaOxinterface layer), and Ga concurrently diffuses from the GaOxinterface layer toward the SiO2, enhancing the crystalline qualityof the interfacial GaOx. Notably, oxygen diffusion from dielectriclayers such as SiO2 and HfO2 toward GaN, and Ga diffusion fromGaOx interface layers toward SiO2 during PDA have beenconfirmed.14,21,22 On the basis of this proposed mechanism, weconceived a simple and effective method for improving the di-electric/GaN interface properties: a dummy SiO2 process in whichSiO2 deposited onto GaN would enhance the crystalline quality ofthe GaOx interface layers as follows. First, a SiO2 layer is depositedonto GaN, followed by PDA, which enhances the GaOx crystallinequality, as previously mentioned. The PDA temperature was set at800 °C to diffuse unstable Ga from the GaOx interface layers towardthe SiO2. Second, the SiO2 layer is removed using a buffered HFsolution because the SiO2 quality is lowered as a result of thediffused Ga.23 Third, a dielectric layer is deposited again to fabricatethe MOS device. In this process, the initially deposited SiO2functions as a sacrificial layer; such layers are typically generatedby sacrificial oxidation in the case of Si or SiC.24 In the presentstudy, we found that the flat-band voltage (Vfb) shifts that occurduring positive-bias stress (PBS) tests were considerably reduced indevices fabricated using this process, suggesting that the crystallinequality of the GaOx interface layer was increased, as expected.ExperimentalFigure 1 shows the process flow for the proposed method. Wefabricated Pt/Al2O3/GaN MOS capacitors according to this processflow to confirm the effectiveness of the proposed method. Initially, a5 μm-thick Si-doped n− GaN homoepitaxial layer with a carrierconcentration of 2× 1016 cm−3 was grown on a free-standing n+GaN(0001) wafer via metal-organic vapor phase epitaxy. The carrierconcentration and dislocation density in the wafer were1× 1018 cm−3 and on the order of 106 cm−2, respectively. Thewafer was subsequently cleaned with a H2SO4–H2O2 mixture,followed by treatment with a buffered HF solution for 30 s. Notethat the presence of a crystalline native oxide layer with a thicknessof ∼1 nm was confirmed after the GaN film was cleaned with theH2SO4–H2O2 mixture.17,18 We also confirmed that buffered HFhardly etched β-Ga2O3 (at a rate of approximately 1.4–2.2 nm h−1);therefore, crystalline native oxide layer was considered to remain onthe GaN after the treatment with buffered HF solution for 30 s. Threedifferent processes were then applied to the samples in parallel. Inthe first process, referred to as the standard process, the sample wasnot subjected to further treatment. In the second process, referred toas the pre800C process, the sample was annealed at 800 °C for 300 sunder a flowing N2 atmosphere in a rapid thermal annealing (RTA)system. In the third process, referred to as the dummy process, a5 nm-thick SiO2 layer was deposited on the sample via plasma-enhanced atomic layer deposition (PE-ALD) with a precursor of tris(dimethylamino)silane at 300 °C. After PDA at 800 °C for 300 sunder a flowing N2 atmosphere in an RTA system, the SiO2 layerwas removed with buffered HF solution. Note that the N2 pressureand flow rate were 0.1 MPa (1 atm) and 0.3 slm, respectively, in thepre800C and dummy processes. Immediately after these threeprocedures, a 10 nm-thick Al2O3 layer was deposited onto theGaN via ALD at 300 °C using trimethylaluminum as a precursor andH2O as an oxidant gas. As circular gate electrodes, a 100 nm-thick Ptlayers (∼100 μm in diameter) was deposited onto the Al2O3 layerthrough a shadow mask via electron-beam deposition, followed bythe deposition of a Ti (20 nm)/Pt (100 nm) Ohmic contact on thebackside of the substrate to form a vertical capacitor. Post-metallization annealing (PMA) was finally performed at 300 °CzE-mail: IROKAWA.Yoshihiro@nims.go.jp; NABATAME.Toshihide@nims.go.jpECS Journal of Solid State Science and Technology, 2024 13 085003https://orcid.org/0000-0002-6531-4356http://creativecommons.org/licenses/by/4.0/http://creativecommons.org/licenses/by/4.0/https://doi.org/10.1149/2162-8777/ad6fd2https://doi.org/10.1149/2162-8777/ad6fd2mailto:IROKAWA.Yoshihiro@nims.go.jpmailto:NABATAME.Toshihide@nims.go.jphttps://crossmark.crossref.org/dialog/?doi=10.1149/2162-8777/ad6fd2&domain=pdf&date_stamp=2024-08-28for 5 min under a N2 flow in an RTA system.25 The surfaces of theGaN samples after the standard and dummy processes werecharacterized by atomic force microscopy (AFM) before Al2O3was deposited. In addition, the GaOx layers on the GaN surfaceswere investigated by X-ray photoemission spectroscopy (XPS) usingmonochromatized Al Kα X-ray radiation (hν= 1486.6 eV) with anenergy resolution of 1 eV or better. For samples prepared by thedummy process, secondary-ion mass spectrometry (SIMS) analyseswere carried out using O2+ primary ion bombardment with anenergy of 1.5 keV before the SiO2 layers were removed with abuffered HF solution, where positive atomic ions were monitored forthe Ga signals (both 69Ga and 71Ga were monitored to confirm thatthe signals were due to real Ga and not from a mass interference).For fabricated Pt/Al2O3/GaN MOS capacitors, the capacitance–-voltage (C–V) characteristics were evaluated using a semiconductordevice parameter analyzer (B1500A, Agilent) at room temperatureunder dark conditions.Results and DiscussionWe first acquired AFM images of the GaN surfaces after thestandard and dummy processes (Fig. 2a). The surface of the GaNsample after the dummy process was as smooth as that after thestandard process, with the dummy GaN exhibiting a root meansquare (RMS) surface roughness of 0.12 nm over a 1.0× 1.0 μm2field of view, suggesting that the dummy process did not lead to anysurface roughness. We next used XPS to characterize the differencesbetween the GaOx layers on the GaN surfaces following the standardand dummy processes before Al2O3 deposition. Figure 2b shows Ga3d core-line XPS spectra of the GaN surfaces after the standard (top)and the dummy (bottom) processes. The binding energy in the XPSspectra is displayed with reference to that of the N 1 s peak(397.4 eV). As shown in Fig. 2b, the Ga 3d peaks were deconvolutedinto two components: a Ga–N bond peak at 19.6 eV and a Ga–Obond peak at 20.4 eV. The Ga–O signal after the dummy process(bottom) is slightly stronger than that after the standard process(top); therefore, the GaOx layer on the GaN surface of the dummysample may be denser and/or thicker than that on the GaN surface ofthe standard sample. We used SIMS to measure the diffusion of Gain the SiO2 layer after the annealing step in the dummy process;Fig. 2c shows the depth profile of the Ga concentration. Datacorresponding to annealing temperatures in the range 600 –900 °Care displayed for comparison, along with the data for an as-grownsample. As can be seen, no noticeable Ga diffusion into SiO2 wasobserved for samples annealed at temperatures of less than 700 °C.By contrast, the depth profiles for samples annealed at 800 or 900 °Cshow Ga diffusion to some extent. Given the results of a previousstudy,14 we assume that unstable Ga atoms diffused from the GaOxinterface layer in samples annealed at 800 or 900 °C. Meanwhile, wehave not obtained SIMS data for N atoms. According to the XPSdata shown in Fig. 2b, the GaOx interface layer could be thicker afterthe 800 °C annealing since the Ga-O signal after the annealingslightly stronger than that after the standard process, suggesting thatsome N atoms in GaN are replaced by O atoms diffused from theSiO2 layers. Therefore, N atoms could diffuse from GaN towardSiO2.We conducted C–V measurements to investigate the interfaceproperties of the fabricated Pt/Al2O3/GaN MOS capacitors. Figure 3shows the results for devices fabricated on GaN samples using (a)the standard, (b) the pre800C, and (c) the dummy processes. Thegate bias was swept from inversion to accumulation and back toinversion with various measurement frequencies ranging from 1 kHzto 1 MHz to reveal hysteresis. Notably, the measurement voltagewas swept within a 2.0 V range with reference to the determined Vfband the ideal Vfb, which was defined as the metal–semiconductorwork function difference and was calculated to be 1.04 V for aneffective Pt work function of 5.23 eV, an electron affinity of 4.1 eVfor GaN, 26 and an intrinsic carrier concentration of 2× 10−11 cm−3for GaN.27 As for the effective Pt work function, we deduced thevalue from a plot of Vfb as a function of oxide thickness forPt/SiO2/Si capacitors.28 As shown in Figs. 3a–3c, no noticeablehysteresis was observed in any of the bidirectional sweeps; however,in the magnified views of the regions near Vfb, a small amount ofhysteresis was confirmed, especially in the insets of Figs. 3a and 3b.We carried out C–V measurements with various voltage amplitudesat 1 MHz; the results are summarized in Fig. 3d, which shows the Vfbhysteresis as a function of the applied |V−Vfb| at 1 MHz. Note thatthe maximum applied |V−Vfb| was 4 V, which corresponds to 4 MVcm−1. As shown in Fig. 3d, Vfb hysteresis was negligible for all ofthe samples prepared using the three processes when the applied|V−Vfb| was less than 2.5 V. However, when the applied |V−Vfb|was greater than 3.0 V, the Vfb hysteresis rapidly increased forsamples prepared using the standard and pre800C processes. Inparticular, the pre800C samples exhibit the largest Vfb hysteresisamong the samples prepared using the three processes, likely as aFigure 1. Process flow for fabricating MOS capacitors.Figure 2. (a) AFM images of GaN surfaces after the standard (left) and thedummy (right) processes. (b) Ga 3d core-line XPS spectra of GaN surfacesafter the standard (top) and the dummy (bottom) processes. (c) Ga depthprofile in SiO2/GaN subjected to various PDA conditions, as determined bySIMS measurements.ECS Journal of Solid State Science and Technology, 2024 13 085003result of degradation of the surface after annealing at 800 °C.However, the dummy process drastically reduced the Vfb hysteresis,suggesting that the dummy process decreases the density ofAl2O3/GaN interface traps by enhancing the crystalline quality ofthe interfacial GaOx. We note an issue regarding Vfb: the Vfb forsamples prepared using the dummy process slightly shifts in thenegative voltage direction compared with that for samples preparedusing the standard and pre800C processes (Figs. 3a–3c). The sametrend has been reported for SiO2/GaN MOS capacitors subjected toPDA.14,29–31 To investigate this phenomenon, we acquired the Vfbvalues for Pt/Al2O3/GaN MOS capacitors with various Al2O3thicknesses, prepared using the dummy process (Fig. 3e). If chargesexist at the Al2O3/GaN interface, a plot of Vfb vs Al2O3 thicknessshould show a slope that is proportional to the charge density.28However, since this plot is not linear, we therefore assume that thenegative-bias-direction Vfb shift for a sample obtained using thedummy process does not originate from charges at the Al2O3/GaNinterface. In addition, charges in the Al2O3 layers were notresponsible for the Vfb shift because all the Al2O3 layers weredeposited under the same conditions in all three of the investigatedprocesses. A possible explanation is GaN surface modification. Thatis, the GaN surfaces might no longer be GaN after the samples withSiO2 layers are annealed; they might have transformed into GaON,as reported previously,32,33 where the ideal Vfb might be less than1.04 V. The Al2O3/GaN interface properties were further investi-gated using conductance measurements (Fig. 3f).34 As shown inFig. 3f, Dit for samples prepared using the standard and dummyprocesses was found to be on the order of 1011 cm−2 eV−1, and thatfor samples prepared using the pre800C process was found to be inthe lower 1012 cm−2 eV−1 range. In contrast to the drastic differencein Vfb hysteresis between the standard and dummy processes(Fig. 3d), the Dit values for samples prepared using these twoprocesses are similar. This is attributable to the difference in trapenergy levels; that is, the Dit shown in Fig. 3f corresponds toshallower energy levels and the Vfb hysteresis shown in Fig. 3dreflects deeper energy levels. The higher Dit for samples prepared viathe pre800C process can be explained by the degraded surface afterannealing at 800 °C, as previously mentioned. In other words, GaNwas annealed at 800 °C for 300 s in N2 without any encapsulationlayers in the pre800C process. We speculate that the native oxidelayers on GaN are degraded by the annealing, leading to the higherDit at the Al2O3/GaN interface. We also confirmed that HF hardlyetched β-Ga2O3 and consider that HF treatment has little effect onthe native oxide layers on GaN; therefore, the higher Dit at theAl2O3/GaN interface in the pre800C process does not relate to theHF treatment. For the same reason, if the GaN undergoes HFtreatment after the pre800C process, we speculate that the Dit at theAl2O3/GaN interface would not decrease.Finally, we performed PBS tests to evaluate the effectiveness ofthe proposed method in terms of device reliability. Figure 4 showsVfb shifts at a measurement frequency of 1 MHz as a function ofstress time under various stress conditions for Al2O3/GaN MOScapacitors fabricated on GaN samples via the three processes. InFig. 4, various bias voltages, V−Vfb, ranging from 2.0 to 4.0 V wereapplied for the duration indicated on the abscissa. The same trendobserved in Fig. 3d is found. As shown in Fig. 4, the stronger theapplied bias and the longer the stress time, the larger the Vfb shift forall of the samples, indicating that the time constant and energy depthfor traps are diversified. Among samples prepared using the threeprocesses, those prepared via the dummy process display distinctstability irrespective of the applied bias and stress time, presumablybecause of the enhanced crystalline quality of the interfacial GaOx.However, the pre800C process resulted in the worst Vfb stability,which we attribute to the degraded surface after annealing at 800 °C.Figure 3. C–V characteristics for Al2O3/GaN MOS capacitors fabricated on GaN samples via (a) the standard, (b) the pre800C, and (c) the dummy processes. In(a)–(c), the measurement voltage was swept within a 2.0 V range with reference to the determined Vfb, and the insets show magnified views of the regions nearVfb. (d) Summary of the obtained Vfb hysteresis as a function of the applied |V−Vfb| at 1 MHz. (e) Vfb at a measurement frequency of 1 MHz, plotted as a functionof the Al2O3 thickness for Al2O3/GaN MOS capacitors fabricated on GaN samples via the dummy process. (f) Dit distribution for Al2O3/GaN MOS interfacesfabricated via three different processes. Here, black squares, blue triangles, and red circles show Dit values for samples fabricated using the standard process, thepre800C process, and the dummy process, respectively.ECS Journal of Solid State Science and Technology, 2024 13 085003ConclusionsWe proposed a simple and effective method referred to as thedummy SiO2 process for improving dielectric/GaN interface proper-ties. The process was found to drastically increase Vfb stability,possibly as a result of improved GaOx interfaces. This method canbe applied not only to Al2O3/GaN but also to other dielectric/GaNsystems.AcknowledgmentsThis research was supported in part by the Ministry of Education,Culture, Sports, Science and Technology, Japan (MEXT), through its“Creation of Innovative Core Technology for Power Electronics”Program Grant Number JPJ009777 and ARIM (JPMXP1223NM5088).ORCIDYoshihiro Irokawa https://orcid.org/0000-0002-6531-4356References1. T. Kachi, 2018 IEEE International Electron Devices Meeting Proceedings, 452(2018).2. T. Oka, Jpn. J. Appl. Phys., 58, SB0805 (2019).3. K. Ito, S. Iwasaki, K. Tomita, E. Kano, N. Ikarashi, K. Kataoka, D. Kikuta, andT. Narita, Appl. Phys. Express, 16, 074002 (2023).4. Y. Ichikawa, K. Ueno, T. Kondo, R. Tanaka, S. Takashima, and J. Suda, Jpn. J.Appl. Phys., 63, 02SP31 (2024).5. S. J. Pearton, F. Ren, A. P. Zhang, and K. P. Lee, Mater. Sci. Eng. R, 30, 55 (2000).6. H. C. Casey, Jr, G. G. Fountain, R. G. Alley, B. P. Keller, and S. P. DenBaars, Appl.Phys. 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Y. Irokawa, K. Mitsuishi, T. Izumi, J. Nishii, T. Nabatame, and Y. Koide, ECS J.Solid State Sci. Technol., 12, 055007 (2023).34. K. Yuge, T. Nabatame, Y. Irokawa, A. Ohi, N. Ikeda, L. Sang, Y. Koide, andT. Ohishi, Semicond. Sci. Technol., 34, 034001 (2019).Figure 4. Vfb shifts at a measurement frequency of 1 MHz as a function the stress time under various stress conditions for Al2O3/GaN MOS capacitors fabricatedon GaN samples using (a) the standard, (b) the pre800C, and (c) the dummy processes. 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