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Xiujun Wang, Sannian Song, Haomin Wang, Tianqi Guo, Yuan Xue, Ruobing Wang, HuiShan Wang, Lingxiu Chen, Chengxin Jiang, Chen Chen, Zhiyuan Shi, Tianru Wu, Wenxiong Song, Sifan Zhang, [Kenji Watanabe](https://orcid.org/0000-0003-3701-8119), [Takashi Taniguchi](https://orcid.org/0000-0002-1467-3105), Zhitang Song, Xiaoming Xie

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[Minimizing the Programming Power of Phase Change Memory by Using Graphene Nanoribbon Edge‐Contact](https://mdr.nims.go.jp/datasets/b29c1cb9-f0c2-4ec7-9767-77f18ebdc04b)

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Minimizing the Programming Power of Phase Change Memory by Using Graphene Nanoribbon Edge‐ContactRESEARCH ARTICLEwww.advancedscience.comMinimizing the Programming Power of Phase ChangeMemory by Using Graphene Nanoribbon Edge-ContactXiujun Wang, Sannian Song, Haomin Wang,* Tianqi Guo, Yuan Xue, Ruobing Wang,HuiShan Wang, Lingxiu Chen, Chengxin Jiang, Chen Chen, Zhiyuan Shi, Tianru Wu,Wenxiong Song, Sifan Zhang, Kenji Watanabe, Takashi Taniguchi, Zhitang Song,*and Xiaoming XieNonvolatile phase-change random access memory (PCRAM) is regarded asone of the promising candidates for emerging mass storage in the era of BigData. However, relatively high programming energy hurdles the furtherreduction of power consumption in PCRAM. Utilizing narrow edge-contact ofgraphene can effectively reduce the active volume of phase change material ineach cell, and therefore realize low-power operation. Here, it demonstratesthat the power consumption can be reduced to ≈53.7 fJ in a cell with≈3 nm-wide graphene nanoribbon (GNR) as edge-contact, whosecross-sectional area is only ≈1 nm2. It is found that the polarity of the biaspulse determines its cycle endurance in the asymmetric structure. If a positivebias is applied to the graphene electrode, the endurance can be extended atleast one order longer than the case with a reversal of polarity. In addition, theintroduction of the hexagonal boron nitride (h-BN) multilayer leads to a lowresistance drift and a high programming speed in a memory cell. The workrepresents a great technological advance for the low-power PCRAM and canbenefit in-memory computing in the future.X. Wang, S. Song, H. Wang, T. Guo, Y. Xue, R. Wang, H. Wang, L. Chen,C. Jiang, C. Chen, Z. Shi, T. Wu, W. Song, S. Zhang, Z. Song, X. XieState Key Laboratory of Functional Materials for InformaticsShanghai Institute of Microsystem and Information TechnologyChinese Academy of Sciences865 Changning Road, Shanghai 200050, P. R. ChinaE-mail: hmwang@mail.sim.ac.cn; ztsong@mail.sim.ac.cnX. Wang, S. Song, H. Wang, Y. Xue, R. Wang, H. Wang, C. Chen, T. Wu,W. Song, Z. Song, X. XieCenter of Materials Science and Optoelectronics EngineeringUniversity of Chinese Academy of SciencesBeijing 100049, P. R. ChinaThe ORCID identification number(s) for the author(s) of this articlecan be found under https://doi.org/10.1002/advs.202202222© 2022 The Authors. Advanced Science published by Wiley-VCH GmbH.This is an open access article under the terms of the Creative CommonsAttribution License, which permits use, distribution and reproduction inany medium, provided the original work is properly cited.DOI: 10.1002/advs.2022022221. IntroductionPhase-change random access memory(PCRAM) is a promising circuit-buildingblock for non-von Neumann computingarchitectures by combining storage andcomputing functions. It is equipped withdesirable properties for nonvolatile, highdevice density, high programming speeds,and long switching lifetime.[1,2] These prop-erties are the key enablers of componentsfor in-memory computing in highly data-centric applications. Therefore, in terms ofmaterials and device structure, new phase-change devices are highly desired to enablehigh throughput, area-efficient, and energy-efficient information processing. Bothcapitalizing on new phase change materials(PCMs)[3] and applying an incubationfield[4] can lead to higher operating speedwhile stacking phase-change multilayeredX. Wang, H. Wang, H. Wang, L. Chen, C. Jiang, C. Chen, Z. Shi, T. Wu,X. XieCAS Center for Excellence in Superconducting Electronics (CENSE)Shanghai 200050, P. R. ChinaC. Jiang, X. XieSchool of Physical Science and TechnologyShanghaiTech UniversityShanghai 201210, P. R. ChinaK. WatanabeResearch Center for Functional MaterialsNational Institute for Materials Science1-1 Namiki, Tsukuba 305-0044, JapanT. TaniguchiInternational Center for Materials NanoarchitectonicsNational Institute for Materials Science1-1 Namiki, Tsukuba 305-0044, JapanAdv. Sci. 2022, 9, 2202222 © 2022 The Authors. Advanced Science published by Wiley-VCH GmbH2202222 (1 of 8)http://crossmark.crossref.org/dialog/?doi=10.1002%2Fadvs.202202222&domain=pdf&date_stamp=2022-07-18www.advancedsciencenews.com www.advancedscience.comheterostructure could extend switching lifetime.[5] The greatestchallenge faced by PCRAM at this moment is how to reduceits power consumption further. There are several ways to re-duce the power consumption of cells: including manipulating theelectrodes,[6,7] exploiting new materials,[8,9] and designing devicearchitecture.[10]The scaling on phase-change cells not only can enable the in-tegration of more memory devices, but also reduce the program-ming energy. The conventional memory cell exhibits a relativelyhigh power consumption due to its large contact area betweenPCM and the heating electrode.[11] The cutting-edge technolo-gies in the semiconductor industry can scale memory cells onlydown to sub-7-nm, but the contact area is still in tens of nm2.Creating a gap in carbon nanotube can decrease the active vol-ume of phase change materials by orders and then reduce thepower consumption.[6,12–14] Nevertheless, the technique needs ex-tensive skills and complex processes in both nano-gap fabricationand deposition of phase change material. Using blade electrodesis another approach to reduce the materials needed to be heatedup, and then consume less energy. However, the cross-sectionalarea of the memory cells with the most advanced blade electrodestill exceeds 40 nm2.[7,15]Graphene is a two-dimensional semi-metal with a thickness ofa single atom (≈0.335 nm).[16,17] It can make 1D electrical contactwith other materials by edge-contact.[18,19] In addition, grapheneis chemically inert and thermally stable, with a current-carryingcapacity of more than 109 amps per square centimeter.[20,21] Themerits are highly desired in electrodes for phase change pro-gramming. Therefore, graphene can serve as the thinnest blade-electrode for PCRAM cells in nature. Recently, lateral PCRAMcells with patterned GNR electrodes were demonstrated at Stan-ford University.[22] However, the power consumption of the cellsis still one order of magnitude greater than those with CNT elec-trodes due to the challenges in process control over the qualityof both GNR–GST interface and GST material. Encapsulation ofGNRs with hexagonal boron nitride (h-BN) flakes can preservetheir intrinsic properties by keeping them from the ambient en-vironment even under programming operation. Besides, the h-BN flake in a suitable thickness can serve as a “heat sink” in pro-gramming because of its high in-plane thermal conductivity.[23,24]Bringing both GNR and h-BN flakes to contact PCMs with theiredges builds up a new design for the structure of PCRAM cells.In this report, we adapt the edges of graphene nanostructureas blade-contact to memory cells. Here, Ge2Sb2Te5 (GST) is se-lected as PCM as it has been widely used in PCRAM and ex-tensively studied. The dimensions of the cells are defined bythe width of edge-contact of graphene (≈3 nm to 2 μm). As theedge is the location with the highest E-field and Joule heating ingraphene, switching of PCMs occurs only near the edge-contacts.It is found that the switching speed could reach 5 ns in a mem-ory cell with graphene edge-contact. Its cycle endurance reachesabout 6 × 106 if a proper bias polarity is applied. The power con-sumption of the memory cell decreases to ≈53.7 fJ when the con-tact width decreases to ≈3 nm. The corresponding cross-sectionalarea of the edge-contact is only ≈1 nm2. Its operation durationis close to 3 × 105, which allows reliable iterative programmingoperations. In addition, a D flip-flop prototype working under2.5 MHz was demonstrated in a memory cell with graphenenanoribbon (GNR) edgecontact. The detailed process for fabri-cation of a memory cell with edge-contact is described in Experi-mental Section and Supporting Information (Figure S1, Support-ing Information).2. Results and DiscussionFigure 1a shows a schematic of a memory cell by using grapheneedge as 1D contact. Its AFM image is given on the left ofFigure 1b. The width of edge-contact is about 2 μm. A high-resolution transmission electron microscopy (HRTEM) imageshows a cross-sectional view of edge-contact on the right of Fig-ure 1b. The blue and green areas represent the capping and bot-tom layer of h-BN, respectively. The grey contrast comes fromtheir different lattice orientations. The position of the graphenelayer is also pointed out in Figure 1b. Figure 1c shows theresistance-temperature relationship of GST, which exhibits acrystallization transition at the temperature of ≈155.7 °C. Thedata retention of the RESET state in GST cells is expected to be≈80.2 °C for 10 years by Arrhenius fitting (Figure S2, Support-ing Information). As shown in Figure 1d, the selected area elec-tron diffraction (SAED) pattern of the GST film exhibits that thenanocrystal grains exhibit a face-centered cubic structure, whichwas further confirmed with HRTEM images.Bilayer graphene (BLG), monolayer graphene (MLG), andGNR of different widths are used as the edge-contact of mem-ory cells. The narrowest pattern of graphene defined by lithogra-phy is a width of ≈30 nm. In order to narrow the contact further,GNRs embedded in h-BN[27] were used as edge-contact to PCMs.The width of GNRs used here is less than 10 nm. As the SETenergy ESET is almost three orders lower than the RESET energyERESET, it is always ignored when calculating the power consump-tion of memory cells.[28] Before measurement, the memory cellswere annealed at ≈260 °C in order to set the initial state of GSTready for the test to a low resistance state (LRS, also known as ONstate). Subsequently, a series of current pulses with a fixed dura-tion (100 ns) were sourced to the cell via graphene edge-contactwith the magnitude of the pulses gradually increasing. Simulta-neously, the resistances of memory cells were recorded. And theresults are shown in the inset of Figure 2a. The action to set thecell from LRS to a high resistance state (HRS, also called OFFstate) is marked as RESET, this switching is corresponding tothe quick melting and quenching of GST, turning the materialinto the amorphous phase. Here, the minimum current pulseswitching the cell to HRS is defined as RESET current. (Moreresults about RESET current are shown in Figure S3, Support-ing Information) The variation of RESET current with respect tothe width of edge-contact is plotted in Figure 2a. It is found thatRESET current monotonously decreases with the shrink of con-tact width, while the cell resistance measured increases. It is alsofound that the RESET current of memory cells with BLG contactis almost twice that of cells with MLG contact in the same width.The RESET current measured is ≈11 μA in the cell with ≈30 nm-wide edge-contact of MLG. And the RESET current in a pulse of100 ns obtained is ≈0.9 μA in a memory cell with a ≈3 nm-wideGNR edge-contact.Subsequently, the contact-area dependence of power con-sumption (E =Δt∫0IVdt) of each memory cell is extracted, whereI represents RESET current, V is RESET voltage, and Δt is a timeAdv. Sci. 2022, 9, 2202222 © 2022 The Authors. Advanced Science published by Wiley-VCH GmbH2202222 (2 of 8)www.advancedsciencenews.com www.advancedscience.comFigure 1. Memory cell with graphene edge-contact. a) Schematic of the cell. b) AFM image of a memory cell where palladium (Pd), GST, and h-BN/Gr/h-BN are painted with gold, brown and cerulean, respectively. The scale bar is 1 μm. The HRTEM image on the right shows a cross-sectional view of theedge-contact, the scale bar is 10 nm. c) The resistance variation of a 60 nm-thick GST film in a cycle of annealing. The heating and cooling rates are ≈20and ≈100 °C min−1, respectively. d) TEM investigation on another GST film annealed at ≈260 °C, and the insert shows the corresponding SAED pattern.Zoom-in views on two specific crystal grains framed are given on the right.Figure 2. Scaling trend of power consumption. a) RESET current versus width of edge-contact in memory cells. Insert shows RESET process driven bycurrent pulses in the memory cells with different edge-contact. b) Power consumption as a function of the contact area. The yellow circle, blue square,and red triangle represent the results from the 74 cells with edge-contact of BLG (26 pieces), MLG (29 pieces), and GNR (19 pieces), respectively. Theother symbols in gray are data on power consumption adapted from literature.[5,6,12,13,25,26]symbol for pulse duration. Transient RESET voltage measuredis recorded once the cell completes the RESET action. The re-lationship of power consumption versus contact area in mem-ory cells is plotted in Figure 2b. The power consumption of low-power PCRAMs reported in literature was also included for com-parison. It is found that the power consumption decreases withthe contact area. The power consumption decreases to ≈53.7 fJfor the cell with ≈3 nm-wide GNR edge-contact (The measure-ment, extraction, and calculation method were detailed in FigureS4, Supporting Information). The value is obviously smaller thanthose reported in the literature, enabled by the tiny amount ofGST addressed with the GNR electrode. The decrease in powerconsumption attributes to the shrinking of the contact area be-tween the electrodes and GST.Cycle endurance is extensively investigated in the cells withedge-contact. The voltage for the operation of “Read” always iskept at 0.1 V unless otherwise noted. The cells using MLG/GNRas edge-contact are physically asymmetric in their device struc-ture. The asymmetry in device structure has a significant influ-ence on the device endurance under different voltage polarities.A schematic of the cell and measurement setup is shown in Fig-ure 3a. The results of cycle-endurance measured in ≈1 μm MLGedge-contact cells and GNR edge-contact cells in ≈3 nm width areplotted in Figure 3b,c, respectively. The memory cell with ≈1 μmMLG edge-contact (#MLG 74) exhibits an endurance close to 6 ×106 (Figure 3b), and the ≈3 nm GNR edge-contact memory cell(#MLG 103) shows an endurance up to 3 × 105 when the voltagepulse is applied from Port I to II (Figure 3c). Meanwhile, whenAdv. Sci. 2022, 9, 2202222 © 2022 The Authors. Advanced Science published by Wiley-VCH GmbH2202222 (3 of 8)www.advancedsciencenews.com www.advancedscience.comFigure 3. Endurance dependence on voltage polarity in the cells with an asymmetric structure. a) Schematic of the cell structure and measurementlayout. b) Endurance test in the cells with MLG edge-contact. The data shown in the upper diagram were obtained with 1.5 V/100 ns SET pulse and2.5 V/100 ns RESET pulse in a cell (#MLG 74) with ≈1 μm wide MLG edge-contact, while those shown in the bottom diagram were taken with 1.5 V/100 nsSET pulse and 2.8 V/100 ns RESET pulse in another cell (#MLG 55) in a similar configuration. c) Endurance investigation of a cell with ≈3 nm wide GNRedge-contact. The results in the upper diagram were obtained with 0.5 V/100 ns SET pulse and 1 V/100 ns RESET pulse (#GNR 103), while those shownin the bottom diagram were taken with 0.6 V/100 ns SET pulse and 1.2 V/100 ns RESET pulse in another cell (#GNR 108) in a similar configuration. Asshown in (b) and (c), voltage pulse applied from Port I→CUT→II leads to long endurance and “Stuck RESET” failure as shown in the cell while applyinga voltage pulse from Port II to I through CUT results in short endurance and failure in a low resistance state (“Stuck SET”) in both cells. d,e) Statisticson the cycle endurance for MLG and GNR edge-contact memory cells, respectively. It is found that the cycle endurance exhibits obvious the polarity ofbias pulse in the asymmetric devices. If a positive bias was applied to the graphene electrode, the endurance could be extended at least one order longerthan the case with a reversal of polarity.a pulse voltage was applied from Port II to I through CUT, theendurances become just around 105, as shown in Figure 3b,c. Itis also noted that the voltage polarity has a strong effect on failuremodes. When voltage pulse was applied from Port I → CUT → II,the cell fails in a high resistance state (“Stuck RESET”). Reversalof voltage polarity always leads to the failure of “Stuck SET”.A systematic statistical investigation on cycle endurance wasalso carried out, and the results are shown in Figure 3d,e, respec-tively. As shown in Figure 3d,e a relatively long endurance canbe achieved in most of the cells with edge-contact if the voltagepulse was applied from Port I to II through CUT. Cells appliedwith voltage pulse direction (Port I → CUT → II) are all found tofail in “Stuck RESET”, while those in the reversal of voltage polar-ity fail in “Stuck SET” (See Figure S6, Supporting Information).Figure S7, Supporting Information shows a cross-sectional TEMimage of the cell after “Stuck RESET” failure. The void, which isprofiled by the white dash line in Figure S7, Supporting Infor-mation, is found at the contact between graphene-edge and GST.The appearance of a void is normally regarded as the signaturefor “Stuck RESET”.A cross-sectional TEM image and elemental EDS maps of thecell with “Stuck SET” failure after the endurance test was shownin Figure S8, Supporting Information. As shown in Figure S8f–h, Supporting Information, the signals of Ge, Sb, and Te ele-ments extended into the Van der Waals (vdW) interface of h-BN/graphene by emigration. As shown in Figure S8i, SupportingInformation, the counts of Ge elements are slightly more thanSb and Te in the active region (colored with red). The composi-tion of GST in the gray region of Figure S8i, Supporting Informa-tion is similar to the composition of GST (Figure S8j, SupportingInformation) in the inactive region marked in Figure S8a, Sup-porting Information. This indicates that the size of the active re-gion is ∼10 nm. When the voltage pulse was applied from PortII → CUT → I, elements in GST emigrate into the interlayers ofgraphene/h-BN under the electric and thermal fields, and thenform a small confined active region. In this tiny region, the ele-ment segregation of the GST under the cycle test greatly degradesthe cycle endurance with “Stuck SET” failure.In addition, thermoelectric properties (Peltier and Thomsoneffects) may be one important factor for memory cells becausethermoelectric heating can significantly influence the tempera-ture distribution in the memory cells.[29] If thermoelectric heat-ing exists during programming in PCM cells, it could be a supple-ment to Joule heating. It is possible to qualitatively achieve somesignature of the thermoelectric effects by comparing the differ-ence of RESET voltage under different polarities in the samedevice.[30] In order to compare the effect of the voltage polarity onthe RESET voltage, we carried out the statistical analysis on theAdv. Sci. 2022, 9, 2202222 © 2022 The Authors. Advanced Science published by Wiley-VCH GmbH2202222 (4 of 8)www.advancedsciencenews.com www.advancedscience.comamplitudes of voltage pulse under different polarities in the samememory cell without taking cycle endurance measurements insome devices. As shown in Figure S9b, Supporting Information,little difference was observed in the RESET voltages of the twopolarities. It indicates that thermoelectric heating may not be pro-nounced during programming in the cells with graphene.The resistance drift was also measured in the cells withgraphene edge-contact (Figure S10, Supporting Information),and the coefficient of resistance drift is found to be close to 0.02,which is significantly smaller than that in memory cells withcylinder electrode (v = ≈0.1).[31] In order to explore the main pos-sible reason for the small drift of resistance, we fabricated somememory cells addressed with graphene edge-contact. The differ-ence is that h-BN multilayers were damaged by N2 plasma be-fore assembling vdW heterostructures. As shown in Table S2,Supporting Information, the substrate with high thermal con-ductivity is beneficial to improve the resistance stability of amor-phous GST while it may also lead to an increase in power con-sumption, and therefore sometimes shorten the cycle endurance.The small resistance drift, we believe, may be related to the ex-tremely high in-plane thermal conductivity of graphene[32] andh-BN flakes,[23,24] contacting the active region of phase change.In general, a high thermal conductivity should lead to a fastercooling rate and thus more unrelaxed local structures. And then,reducing the thermal relaxation of GST in the RESET program-ming process will enhance the resistance drift because the un-relaxed local structures will gradually relax after programmingand thereby lead to resistance drift. The normal knowledge failsto provide an explanation on our experiment results. The fallingtime of programming pulses is an important factor to tune theresistance drift by affecting the structural relaxation of the activeregion.In order to verify the influence of falling time on the resistancedrift, we set the falling time to 3, 4, 5, and 6 ns, respectively. “3 ns”is the minimum value that our test system can be set to. How-ever, we did not find obvious dependence of resistance drift onthe falling time. A longer falling time than 6 ns always spoils theamorphous state of the device. In this case, it looks very difficultto achieve a conclusive result about the influence of falling timeof voltage pulse on resistance drift at this moment.It is indeed an interesting issue that is really worth further in-vestigation. Here, we would like to give two possible reasons forthe small resistance drift: 1) Graphene edge-contact reduce thevolume of the active region, and the small active region normallyleads to less stress together with the high thermal conductivityof graphene and h-BN. 2) The weak vdW interactions betweenGST and h-BN or GNR could cause full relaxation of amorphousGST.[33] In contrast, the defective h-BN or SiO2 results in more re-active bonds whose reaction and relaxation may lead to a higherresistance drift.As the nonvolatile memory cells can perform the function ofresistive switching, we demonstrated the logic function of D latchbased on the memory cells with edge-contact. The results areshown in Figure S11, Supporting Information. Figure S11a, Sup-porting Information displays the logic function of the D latch.Input signals can modify the magnitude of output resistance. Itis always expressed as the switching of logic states in the cell.Here, “D”, “Q”, and “Q*” denote input, initial state, and subse-quent state, respectively. Both pulses of high voltage (2.5 V) andHRS are defined as logical “1”, while the pulses of low voltage(1.5 V) and LRS are defined as logical “0”. As shown in FigureS11a, Supporting Information, if no voltage pulse is applied (D =“zero input”), the subsequent state (Q*) remains the initial state(Q). When a voltage pulse in 1.5 V (D = logical “0”) is sourced,the cell switches from the HRS to LRS. Similarly, a voltage pulseof higher amplitude (2.5 V) (D = logical “1”) will switch the cellfrom the LRS to HRS. The voltage for reading the cell resistancealways remains less than 0.1 V unless otherwise noted. The cor-responding truth table and the logic diagram are shown in Fig-ure S11b,c, Supporting Information, respectively. In this design,Q/Q* and input D share the same pin, and they are separated bya switching circuit. The resistance state of the cell (also knownas Q/Q*) can be read if the 1T is open. A small voltage (≈0.1 V)which is applied to read the resistance state of the memory celldoes not affect the state of the cell.On this basis, we prepared a D flip-flop made from a mem-ory cell with GNR edge-contact. The fabrication process for theD flip-flop based on the memory cell with edge-contact of GNR isshown in Figure S10, Supporting Information. Figure 4a showsa schematic and measurement setup for the D flip-flop. Dur-ing operation, L1(connected to GST) and L3 (connected to thegraphite which serves as the back-gate) are selected as the input(D) and the clock signal (CLK), whereas L2 (connected to GNR) isgrounded. To investigate the gate tunability of the cell with GNRedge-contact, a small lateral voltage (0.1 V) was applied throughL1 and L2 to measure the resistance by sweeping Vgate from 0 Vto 5.5 V. Figure 4b shows the resistance of the cell versus Vgate at300 K. The red and black line were measured when the memorycell in HRS and LRS, respectively. It is found that the channel ofthe cell with GNR electrode is in ON-state when Vgate = 0 V andOFF-state when Vgate = 5 V (see the R–Vgate curve in Figure S13a,Supporting Information, the GNR transistor exhibits RH (Vgate =0 V)/RL (Vgate = 5 V) ≈105 at 300 K).In order to test its cycle endurance, we set 0.5 V/1 V asSET/RESET voltage with a pulse width of 100 ns to complete thereversible switch from HRS (≈109 Ω) to LRS (≈107 Ω), as shownin Figure 4c. The memory cell shows a cycle endurance of morethan 104.Figure 4d shows a dynamic logic function of the D flip-flop un-der a clock (CLK) signal of 2.5 MHz. The test conditions are thesame as that in Figure 4c. The input D in a voltage pulse of 0.5 V(1 V) is regarded as logical “0” (“1”). Q and Q⁎ represent the initialand subsequent resistance state of the memory cell, respectively.The LRS of the cell means logical “0” while HRS in the cell isconsidered as logical “1”. When CLK is in 0 V (logical “1”), Q⁎ be-comes logical “0” or “1” regardless of the initial resistance state,by following D. However, when CLK is in 5 V, Q⁎ will not changebut remains in its initial state of Q. The transient change of re-sistance can be measured directly by an oscilloscope, the detailsof measurement are shown in Figure S14, Supporting Informa-tion. It is noted that the switch between two states takes ≈20 ns,greatly shorter than 100 ns of the input pulse. This indicates thatthe excrescent electrical energy converts to the Joule heat with-out causing amorphous–crystalline transitions. The correspond-ing truth table is shown in Figure S15b, Supporting Information.D flip-flop normally takes lots of transistors to implement in thetraditional CMOS technology. Here, the memory cell with GNRedge-contact realized the logic function of a D flip-flop, whichAdv. Sci. 2022, 9, 2202222 © 2022 The Authors. Advanced Science published by Wiley-VCH GmbH2202222 (5 of 8)www.advancedsciencenews.com www.advancedscience.comFigure 4. A prototype of the D flip-flop made from a memory cell with GNR edge-contact. a) Schematics of the prototype and the measurement setup.b) The cell resistance versus gate voltage (Vgate) at 300 K. c) Cycle endurance of the memory cell. Both SET (0.5 V)/RESET (1 V) signals are in a pulsewidth of 100 ns. d) Demonstration of logic functions in the D flip-flop.just is composed of PCMs and a GNR channel. In addition, theD flip-flop is the capability of nonvolatile memory. It could beused to produce low-power arithmetic/logic units in nonvolatilerandom-access memories.3. ConclusionScaling PCRAM cells to low dimensions could produce more newphysics to boost their performance if the GST was engineered orchanged to other PCMs. A cell with edge-contact achieves a SETspeed of ≈6 ns at ≈0.45 V, and it exhibits an ultra-low power con-sumption of ≈53.7 fJ in a high endurance of 3 × 105 when thewidth of contact approaches 3 nm. The power consumption ofeach cell is almost several orders of magnitude lower than that inthe state of art PCRAM cells,[34–36] and even half lower than thatin the cell addressed by a CNT gap.[6] The edge-contact geome-try in PCRAM devices could help explore the dynamic switchingprocess of phase-change material at the atomic level and engi-neer different materials, and then improve their electrical perfor-mance. The asymmetric structure of the memory cell with edge-contact enables a great enhancement of cycle endurance if theproper polarity of bias pulse was applied. In addition, the intro-duction of the h-BN multilayer leads to a low resistance drift anda high programming speed in a memory cell.From an application point of view, the performance of PCRAMcells made from graphene edge-contact allows them to serve asnonvolatile DRAM[37] in the future if their endurance is improvedfurther via engineering PCMs or device configuration. The pro-totype of the D flip-flop with GNR edge-contact (Figure S12, Sup-porting Information) shows obvious practical advantages in en-ergy efficiency compared with PCRAM cells made from silicontransistors. A narrow GNR not only brings the blade contact toPCM but also serves as the channel of a field-effect transistor witha high on/off ratio. Phase change devices with edge-contact ofGNRs have shown their potential as the building blocks of uncon-ventional computing architectures to bypass the von Neumannbottleneck[38,39] and overcome the limits of Dennard scaling.[40]4. Experimental SectionDevice Fabrication: Both h-BN and graphene flakes were preparedfrom their bulks by mechanical exfoliation.[41] A pick-up technique simi-lar to the literature[42] was adapted to sandwich graphene in between twoh-BN layers. And a mask of PMMA resistance was defined by lithographyon the capping h-BN surface. The regions of the heterostructure outside ofthe mask were then etched away to expose the edge of graphene. Pd elec-trodes in a thickness of 50 nm were deposited by a magnetron sputter.After another small window was opened to expose the edge of graphene,the GST material was deposited by the magnetron sputter. A diagram ofthe preparation process is shown in Figure S1, Supporting Information.In order to verify the quality of the electrical contact formed betweenthe graphene edge and Pd, the contact resistances Rc were extracted bythe transfer length method (TLM). The results are shown in Figure S16,Supporting Information, it is found that the Rc is ≈600 Ω μm when Vgate= 0 V at 300 K and varies a little under different temperatures.Adv. Sci. 2022, 9, 2202222 © 2022 The Authors. Advanced Science published by Wiley-VCH GmbH2202222 (6 of 8)www.advancedsciencenews.com www.advancedscience.comThe GNRs were grown by chemical vapor deposition.[27] The fabricationfor the D flip-flop based on the memory cell with edge-contact of GNRis shown in Figure S12a, Supporting Information. A flake of graphite waspeeled onto the silicon substrate with 300 nm SiO2. After that, h-BN, whichwas in suitable thickness (≈50 to 60 nm), was then transferred onto thegraphite. And then a h-BN flake with embedded GNRs was transferredonto the h-BN flake. After that, two metal leads were applied to GNRs whilea metal lead was connected to graphite. Subsequently, a h-BN layer with athickness of ≈20 nm covers the GNR devices and acts as a protective layer.Finally, a window was opened by etching and then the GST with ≈30 nm-thick was deposited into the window to connect the metal lead and GNR.GST Deposition: GST films were deposited by using a sputtering sys-tem (ULVAC JEOL 7800F). The deposition rate was kept at ≈0.6 Å s−1 at20 W RF power to minimize the damage to the GNR or graphene.Electrical Measurement: Before electrical measurement, the memorydevices were annealed at ≈260 °C for 3 min in nitrogen flow using a RTP.Electrical measurements were performed with the combination of a Keith-ley 4200 semiconductor characterization system (SCS), an arbitrary wave-form generator (Tektronix AWG5002B), and two Source Meters (Keithley2400-C and 2602A). The resistance of the device (also known as the state ofthe device) was measured by applying a DC bias of 0.1 V, which would notchange the state of the device. And the transient voltages were recordedby an oscilloscope (Tektronix MDO3032).Raman Spectroscopy Characterization: The number of layers forgraphene was determined by Raman spectroscopy with an excitation lineof 532 nm, and the power of the laser was kept at less than 1 mW.Atomic Force Microscopy (AFM): The thickness of graphite and h-BNwas measured by an AFM (Dimension Icon, Bruker) in tapping mode. Andthe GNRs were located by AFM before encapsulating by a capping layer ofh-BN.TEM and STEM Characterization: The film of GST after annealing at260 °C for 3 min was characterized by TEM (JEOL 2100F). And the cross-sectional edge-contact and the width of GNRs were performed in a doubleCs-corrected TEM/STEM (JEM-ARM300F, JEOL) instrument operated at80 kV.Simulation Calculation: In order to study the heat distribution inphase-change memory cells, a comprehensive 3D finite element modelwas used to analyze the heat distribution in GST, and the classical molec-ular dynamics simulations were used to analyze the heat transport inthe graphene and h-BN multidimensional heterostructure. The details areshown in Figure S17, Supporting Information.Supporting InformationSupporting Information is available from the Wiley Online Library or fromthe author.AcknowledgementsH.W. and X.X. thank J.H. Edgar (Kansas State University, USA) forsupplying partial of the h-BN crystals. X.W. thanks Xiaoyu Liu andHao Wang for assistance in device fabrication. X.W. thank Shilong Lvand Tianjiao Xin (Microstructural Characterization Platform in Shang-hai Institute of Microsystem and Information Technology, ChineseAcademy of Sciences) for lamellae preparation and STEM measure-ment. The authors also thank F. Rao from Shenzhen Univ. for discus-sions.The work was partially supported by: the National Natural Sci-ence Foundation of China (Grant Nos. 91964102, 91964204, 51772317,12004406, 61874129), the Strategic Priority Research Program of Chi-nese Academy of Sciences (Grant No. XDB30000000), the NationalKey R&D program (Grant Nos. 2017YFF0206106, 2017YFA0206101),the Science and Technology Commission of Shanghai Municipality(Grant No. 18511110700, 20DZ2203600), Shanghai Rising-Star Program(A type) (Grant No.18QA1404800), the Shanghai Post-doctoral Excel-lence Program (Grant No. 2021515), the China Postdoctoral ScienceFoundation (Grant Nos. 2017M621563, 2018T110415, 2019T120366,2019M651620, BX2021331, 2021M703338), Shanghai Sailing Program(Grant No. 20YF1456400). Soft Matter Nanofab (SMN180827) of Shang-haiTech University. K.W. and T.T. acknowledge support from the Elemen-tal Strategy Initiative conducted by the MEXT, Japan, Grant Number JP-MXP0112101001, JSPS KAKENHI Grant Number JP20H00354 and theCREST(JPMJCR15F3), JST.Conflict of InterestThe authors declare no conflict of interest.Author ContributionsX.W. and S.S. contributed equally to this work. H.W. conceived and de-signed the research. H.W., Z.S. and X.X. supervised the research work.X.W. fabricated the devices and carried out electrical measurements. L.C.,H.S.W., C.C. and C.J. prepared the GNRs. S.S., T.G., Y.X. and R.W. per-formed the sputtering deposition of GST. C.C. and C.J. performed AFMmeasurements. T.G. and Y.X. carried out the TEM measurements. S.Z. andW.S. performed the modeling calculation of heat distribution for mem-ory cell with graphene edge-contact. H.W., S.S. and X.W. analyzed the ex-perimental data and designed the figures. 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