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Jinhyoung Lee, Gunhyoung Kim, Hyunho Seok, Sujeong Han, Hyunwoo Shim, Yoonmi Cha, Sihoon Son, Hyunbin Choi, Magdalena Grzeszczyk, Aleksander Bogucki, Yunseok Choi, Seungil Kim, Hyeonjeong Lee, Chaerin Park, Geonwook Kim, Hosin Hwang, Hyunho Kim, Dongho Lee, Seowoo Son, Geumji Back, Hyelim Shin, Donghwan Choi, Alexina Ollier, Yeon‐Ji Kim, Lei Fang, Gyuho Han, Goo‐Eun Jung, Youngi Lee, Hyeong‐U Kim, [Kenji Watanabe](https://orcid.org/0000-0003-3701-8119), [Takashi Taniguchi](https://orcid.org/0000-0002-1467-3105), Sanghoon Bae, Andreas Heinrich, Won‐Jun Jang, Taesung Kim

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[Monolithically‐Integrated van der Waals Synaptic Memory via Bulk Nano‐Crystallization](https://mdr.nims.go.jp/datasets/75f6829f-fdfa-4bc9-afeb-f599372be6f5)

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Monolithically‐Integrated van der Waals Synaptic Memory via Bulk Nano‐CrystallizationRESEARCH ARTICLEwww.advancedscience.comMonolithically-Integrated van der Waals Synaptic Memoryvia Bulk Nano-CrystallizationJinhyoung Lee, Gunhyoung Kim, Hyunho Seok, Sujeong Han, Hyunwoo Shim,Yoonmi Cha, Sihoon Son, Hyunbin Choi, Magdalena Grzeszczyk, Aleksander Bogucki,Yunseok Choi, Seungil Kim, Hyeonjeong Lee, Chaerin Park, Geonwook Kim,Hosin Hwang, Hyunho Kim, Dongho Lee, Seowoo Son, Geumji Back, Hyelim Shin,Donghwan Choi, Alexina Ollier, Yeon-Ji Kim, Lei Fang, Gyuho Han, Goo-Eun Jung,Youngi Lee, Hyeong-U Kim, Kenji Watanabe, Takashi Taniguchi, Sanghoon Bae,Andreas Heinrich, Won-Jun Jang, and Taesung Kim*Owing to the evolution of data-driven technologies, including the largelanguage models, generative artificial intelligence, autonomous driving, andthe internet of things requires advanced memory technology. However,conventional memory device structures and fabrication process havesignificant limitations for high-density integration. Herein, this study reportsthe monolithically-integrated 1-selector and 1-resistive (1S1R) synapticmemory in van der Waals (vdW) heterostructure, which overcomes theconventional limitations of device integration technologies. Single-step directsynthesis of vdW heterostructure and its corresponding 1S1R cell is fabricatedvia plasma-enhanced lattice-distortion. Scanning-transmission electronmicroscopy, and X-ray photoelectron spectroscopy are correlatively applied toobserve the effects of plasma-enhanced nano-crystallization of bulk vdW VSe2.Furthermore, bipolar resistive switching dynamics have been spatiallyresolved with conductive atomic force microscopy. Furthermore, the artificialvdW heterostructure exhibits the synaptic functionality with interfacial chargeaccumulation at the 2D/3D interface, enabling linear weight updates acrossmultiple resistance states with minimal nonlinearity. In conclusion, it envisionthat the monolithically-integrated 1S1R cell can offers a systematicdevice platform for next-generation vdW electronics and its correspondingmonolithic 3D integration.J. Lee, H. Lee, G. Kim, D. Lee, T. KimSchool of Mechanical EngineeringSungkyunkwan University (SKKU)Suwon-si, Gyeonggi-do 16419, South KoreaE-mail: tkim@skku.eduThe ORCID identification number(s) for the author(s) of this articlecan be found under https://doi.org/10.1002/advs.202510961© 2025 The Author(s). Advanced Science published by Wiley-VCHGmbH. This is an open access article under the terms of the CreativeCommons Attribution License, which permits use, distribution andreproduction in any medium, provided the original work is properly cited.DOI: 10.1002/advs.2025109611. IntroductionIn the era of ubiquitous computing and ar-tificial intelligence (AI), the ever-increasingdemand for real-time, on-site data pro-cessing necessitates the developmentof neuromorphic hardware[1] capableof integrating memory and computingfunctionalities within a single unit. Neuro-inspired devices, particularly memristors,have garnered considerable attention aspromising candidates for edge-computingapplications due to their inherent capabilityto emulate synaptic behaviors with highenergy efficiency[2] and device density.[3]Operating through the modulation ofion migration[4] and defect dynamics,memristors enable multilevel, non-volatileresistance switching, thereby offering a vi-able platform for in-memory computing[5]architectures. Recent advancements in AIand data-centric technologies, includinglarge language models, autonomous vehi-cles, and the Internet of Things (IoT), havefurther accelerated the demand for next-generationmemory systems with enhancedscalability, endurance, and integrationJ. Lee, M. Grzeszczyk, A. Bogucki, A. Ollier, Y.-J. Kim, L. Fang, A. Heinrich,W.-J. JangCenter for Quantum NanoscienceInstitute for Basic Science (IBS)Seoul 03760, South KoreaG. Kim, S. Han, H. Shim, H. Choi, C. Park, H. Hwang, H. Kim, G. Back,H. Shin, D. Choi, T. KimDepartment of Semiconductor Convergence EngineeringSungkyunkwan UniversitySuwon 16419, South KoreaH. SeokResearch Laboratory of ElectronicsMassachusetts Institute of TechnologyCambridge, MA 02139, USAAdv. Sci. 2025, 12, e10961 e10961 (1 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbHhttp://www.advancedscience.commailto:tkim@skku.eduhttps://doi.org/10.1002/advs.202510961http://creativecommons.org/licenses/by/4.0/http://creativecommons.org/licenses/by/4.0/http://crossmark.crossref.org/dialog/?doi=10.1002%2Fadvs.202510961&domain=pdf&date_stamp=2025-08-26www.advancedsciencenews.com www.advancedscience.comcapability. While conventional charge-based memory technolo-gies have benefitted from CMOS scaling,[6] their device architec-tures face intrinsic limitations in terms of power consumptionand integration density.Hence, resistive random-access memory (ReRAM), particu-larly those based on a metal–insulator–metal (MIM) configu-ration, has emerged as a compelling alternative owing to itsstructural simplicity and compatibility with crossbar architec-tures. Despite the promise of ReRAM,most polycrystallinemetaloxide-based memristive devices, such as those utilizing TiOx,[7]TaOx,[8] or HfOx,[9] exhibit significant leakage currents throughgrain boundaries, which result in poor off-state behavior and lowswitching reliability. While the use of amorphous active layers[10]mitigates leakage by eliminating grain boundary[11] pathways,it introduces new challenges in precisely controlling the forma-tion and dissolution of conductive filaments, thereby limiting de-vice uniformity and long-term reliability.[12] Strategies such asdislocation-guided filament confinement[13] in single-crystallineSiGe or field-enhanced conical electrode design have been intro-duced to improve reproducibility[14]; However, the integration ofselector devices is essential to mitigate sneak-path currents incrossbar array architectures, which is a critical prerequisite forenabling the reliable and scalable implementation of resistivememory in very-large-scale integration (VLSI) systems.To address the scalability and integration challenges of pla-nar architectures, the semiconductor industry has increas-ingly focused on three-dimensional heterogeneous integration(3DHI),[15] wherein disparate functional layers, such as memory,logic, and optoelectronics, are vertically stacked to form compact,Y. Cha, G. Han, G.-E. Jung, Y. LeePark Systems Corporation109, Gwanggyo-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do 16229, SouthKoreaH. Seok, S. Son, S. Son, T. KimSKKU Advanced Institute of Nanotechnology (SAINT)Sungkyunkwan UniversitySuwon 16419, South KoreaH. Seok, S. Son, S. Son, T. KimDepartment of Nano Science and TechnologySungkyunkwan UniversitySuwon 16419, South KoreaM. Grzeszczyk, A. Bogucki, A. Ollier, Y.-J. Kim, L. Fang, A. Heinrich,W.-J. JangDepartment of PhysicsEwha Womans UniversitySeoul 03760, South KoreaY. Choi, S. Kim, S. BaeDepartment of Mechanical Engineering and Materials Science andInstitute of Materials Science and EngineeringWashington University in St. LouisMissouri, MO 63130, USAH.-U KimSemiconductor Manufacturing Research CenterKorea Institute of Machinery and Materials (KIMM)Daejeon 34103, South KoreaH.-U KimNano-MechatronicsKIMM CampusUniversity of Science & Technology (UST)Daejeon 34113, South KoreaK. Watanabe, T. TaniguchiNational Institute for Materials Sciencemultifunctional systems. While 3DHI offers significant bene-fits in performance and footprint, its reliance on through-siliconvias and wafer bonding techniques introduces formidable fabri-cation complexities and alignment challenges. As an alternative,monolithic 3D integration (M3D),[16] wherein functional devicelayers are sequentially fabricated and integrated without individ-ual wafer bonding, holds promise for achieving seamless verti-cal integration.[17] However, the mechanical fragility[18] and in-trinsic stress[19] of conventional materials pose serious barriersto the practical realization of M3D integration, especially dur-ing substrate detachment and layer transfer processes.[20] In con-trast, two-dimensional (2D) van der Waals (vdW) materials[3,21]provide a transformative opportunity to overcome these con-straints. Their atomically thin nature, exceptional mechanicalflexibility,[22] and negligible internal stress[23] make them ideallysuited for M3D integration.[24] Moreover, vdW materials main-tain electrical performance[25] comparable to bulk silicon-baseddevices,[26] thereby offering a compelling platform for high-density,[27] low-power memory[28] and logic applications.[29] Nev-ertheless, several limitations have limited the commercial adop-tion of vdW M3D integration. These include i) the difficulty ofachieving precise control over vdW stacking kinetics, ii) the accu-mulation of polymeric residues and mechanical warpage at vdWinterfaces, and iii) the large-area scalability of vdW crystallinity.Herein, we report the monolithically-integrated 1S1R cellin vdW 2D/3D heterostructure, offering the significant break-through of conventional vdW integration technologies. Toachieve the monolithically-integrated 1S1R cell, vdW nano-crystallization has been conducted with Ar +H2S plasma sulfur-ization, inducing the penning effects and ion penetration. Directsynthesis of vdW 2D/3D heterostructure and its corresponding1S1R synaptic device performance were clearly demonstrated,which has not been possible previously. Unlike heterogeneousstacks, this artificial vdW 2D/3D heterostructure can be fabri-cated without additional selector materials or complex 3D stack-ing, which eliminates the interface mismatches and parasiticleakage. The consistent yield and uniform switching behavior ob-served across 50 devices further demonstrate the scalability andreliability of the monolithic 1S1R architecture. Moreover, bipo-lar resistive switching dynamics has been spatially resolved withconductive atomic force microscopy (C-AFM) with the Imax, Imin,and IHRS have been measured as 6.91 × 10−10 A, 1.30 × 10−13A, and 1.27 × 10−10 A. Based on these current values, selectivity(Imax/IHRS) and on/off ratio (Imax/Imin) can be calculated as 5.44× 100 and 5.61 × 103. HRS (high resistance state)/LRS (low re-sistance state) current value statically measured as 0.137 nA inHRS [state “0”], 0.851 nA in LRS [state “1”], and 0.132 nA in HRS[state “0”]. Moreover, plasma sulfurization is processed within atop-down approach, vdW 2D/3D heterostructure can be reliablyfabricated regardless of vdW stacking order, vdW layer numbers,and vdW lattice type. Regarding this systematic expandability, weenvision that our monolithically-integrated 1S1R cell can offersNamiki 1-1, Tsukuba, Ibaraki 305-0044, JapanT. KimDepartment of Nano EngineeringSungkyunkwan UniversitySuwon 16419, South KoreaAdv. Sci. 2025, 12, e10961 e10961 (2 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comFigure 1. Device configuration of monolithically-integrated vdW synaptic memory. a) Schematic illustration of monolithically-integrated vdW synapticmemory, which is constructed with nano-crystallized vdW VSe2 lattice (selector) and bulk vdW VSe2 lattice (resistive memory). Electrodes for resistiveswitching were selected as Platinum (top) and gold (bottom). b) SAED patterns and XPS V 2p spectra of bulk VSe2 and nano-crystallized VSe2, resultingthe nano-crystallization and V─S bonding formation during the Ar + H2S plasma treatment. c) Raman spectra of bulk VSe2 and nano-crystallized VSe2,indicating the decreased A1g peak and increased E2g peak.a systematic platform for next-generation M3D integration andadvanced vdW integration.2. Results and Discussion2.1. Monolithically-Integrated 1S1R Cell in vdW 2D/3DHeterostructureTomonolithically integrate the vdW 2D/3D heterostructure, vdWVSe2 has been nano-crystallized with Ar+H2S plasma-enhancedlattice-distortion techniques. As shown in Figure 1a, Schematicillustration of monolithically-integrated vdW synaptic memory,which is constructed with nano-crystallized vdW VSe2 (selec-tor, 4.49 nm) and bulk vdW VSe2 (resistive memory, 37.3 nm).As nano-crystallized vdW VSe2 and bulk vdW VSe2 operatesas switching medium of conductive filaments, electrodes forresistive switching were selected as platinum (top electrode)and gold (bottom electrode). Selected area electron diffraction(SAED) patterns and XPS V 2p spectra of bulk VSe2 and nano-crystallized VSe2 directly indicating the nano-crystallization andV─S bonding formation during the Ar + H2S plasma treat-ment (Figure 1b). As our previous research revealed the numberof vdW layer of the nano-crystallized vdW materials (Bi2Se3,[30]VSe2[31]) can be precisely controlled with RF plasma powervariation. While the ratio between nano-crystallization (selec-tor) and bulk vdW materials (resistive memory) can be mod-ulated with RF plasma power variation, 1S1R cell functional-ity can be artificial modulated with RF plasma power variation,enabling the potential applications of wafer-scale M3D integra-tion of vdW electronics. Also, Raman spectroscopy of nano-crystallized vdW VSe2 and bulk vdW VSe2 has been conductedin Figure 1c. Owing to the nano-crystallization, A1g peak hasbeen decreased, while E2g peak was reversibly increased. SuchRaman peak redistribution corresponds to the structural recon-struction of nano-crystallized VSe2, validating the grain boundary(decreased E2g peak) and sulfur intercalation (increasedA1g peak)(Figure S1, Supporting Information). In contrast to previous1S1R architectures that rely on multi-step heterogeneous stack-ing and high-temperature growth, our artificial vdW 2D/3D het-erostructure is synthesized via a single-step plasma sulfurization(≈5 min) at room temperature over >cm2 scale. This approacheliminates additional selector deposition and complex 3D stack-Adv. Sci. 2025, 12, e10961 e10961 (3 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comFigure 2. Atomic-scale observation of nano-crystallized VSe2. a) Schematic illustration of nano-crystallization of VSe2, indicating the ion-penning effectsand ion penetration effects of bulk vdWVSe2. Cross-sectional b) STEMand c) TEM image of nano-crystallized VSe2, enabling themonolithically-integratedvdW resistivememory fabrication. d) A sequential cascade of IR spectra, correlating the increasedO-H stretching peak (980 cm−1) with RF plasma power.e) Spatially-resolved GB passivation with PiFM imaging (excitation wavenumber: 980 cm−1). During the Ar + H2S plasma treatment, the H atom andnative oxide chemically bond with an exposed metal atom, directly O─H bonding formation corresponds to the GB passivation effects.ing, thereby reducing fabrication steps by more than 50% com-pared with recent reports,[32] while ensuring high device yieldand uniform switching behavior across 50 devices. The combina-tion of single-step, low-temperature, and wafer-scale fabricationdirectly addresses the scalability challenges of conventional 3Dintegration.2.2. Atomic-Scale Observation of Monolithically-Integrated vdW2D/3D HeterostructureDuring the Ar +H2S plasma treatment, the penning effects andion penetration have been activated (Figure 2a). H2S+ generationdirectly derives the ion Penning effect by the Ar gas and the directionization of H2S as followed Equations (1) and (2).[33]Ar + e− → Ar+ + 2e− (1)Ar+ +H2S → Ar +H2S+ (2)Sufficient electrons in the plasma system can directly ionizeH2S gas to generate H2S+, as shown in Equation (3). But exceptAr gas, it is difficult to generate H2S plasma despite the low ion-ization energy of H2S gas.[34]e− +H2S+ → 2e− (3)Adv. Sci. 2025, 12, e10961 e10961 (4 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comFigure 3. Bipolar resistive switching in vdW 2D/3D heterostructure. a) I–V curve measurements (3 cycles) of vdW 2D/3D heterostructure. A doublehysteresis window has been observed at S1–S3 and S4–S6, which combines the resisitve memory (bulk vdW layers) and selctor (nano-crystallized vdWlayers). The clockwise I–V loop indicates bipolar resistive switching, which is governed by filament formation and rupture, modulated by the selector-enabled current compliance. And its corresponding b) Imin, Imax, IHRS, c) selectivity (ILRS / IHRS), d) on/off ratio (Imax /Imin). e) Time-resolved currentmapping with pulse operation (3 cycles), generating the bipoalr resistive switching. f) Statical evalutation of HRS/LRS state with Vreset (-2.5 V), Vset(+7.5 V) and Vread (+4.0 V), corresponding to the 0.137 nA (HRS [state “0”], Vreset (−2.5 V)→Vread (+4.0 V)), 0.851 nA (LRS [state “1”], Vset (+7.5 V)→Vread(+4.0 V)), and 0.132 nA (HRS [state “0”], Vreset (−2.5 V)→Vread (+4.0 V)).For the precise control of plasma-based sulfurization, gasmixture ratio was settled as Ar gas and H2S gas as 1:1 ratio(50 sccm injection for each gas). Regarding our previous arti-cles, RF power variation can control the penetration vdW layer.Nano-crystallization effect has been observedwith cross-sectionalSTEM imaging (Figure S2, Supporting Information) and energy-dispersive X-ray spectroscopy (EDS) mapping (Figure S3, Sup-porting Information) in Figure 2b,c, exhibiting the nano-grain(lateral dimension as ≈5 nm) formation by lattice-distortion un-der E-field driven ion bombardment. After plasma treatment,vdW interface has been remained clean vdW interface unlikeconventional vdW integration method. To laterally observe thenano-grain distribution and RF plasma power dependency, nano-crystallized VSe2 was sequentially analyzed within PiFM mea-surements. Owing to hydroxy group adsorption at the nano-grain, PiFMmeasurement can spatially detect the O-H stretchingpeak, directly guiding the spatial nano-grain distribution. Addi-tionally, cascade of infrared (IR) spectra with sub-10 nm resolu-tion directly supports the dominance of 980 cm−1 peak withinincreased RF plasma power (Figure 2d). As PiFM spatially re-solves chemical composition with sub-10 nm resolution,[35] pris-tine VSe2 indicates absence of photo-induced force signal. In-creasing the RF plasma power to 300 W, spatial heterogeneityhas been observed with excitation wavenumber 980 cm−1. Spa-tial heterogeneity of photo-induced force was dominantly derivedfrom nano-crystallization. When nano-crystallization has beenAdv. Sci. 2025, 12, e10961 e10961 (5 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comFigure 4. Spatially-resolved resistive switching dynamics via conductive atomic force microscopy. a) Photography and b) schematic illustration of vdWSPM devive setup, configured with biasing tip and probing tip. Bias-dependent topography image of nano-crystallized vdW lattice, resulting in theconductive filaments activation. C-AFM scan has been conducted with sequential “read” and “write” operation ([1] Vreset → [2] Vread [State “0”]→ [3] Vset→ [4] Vread [State “1”]→ [5] Vreset → [6] Vread [State “0”]) c) Spatially-resolved topography and its pixel distribution directly corresponds to the activationof conductive filaments and vertical ionic migration. As current image with Vread (+4.0 V) indicates the HRS [state “0”], LRS [state “1”] has been observedwith (d) Vset (+7.5 V). After Vset (+7.5 V) scanning, LRS [state “0”] retained with Vread (+4.0 V) scan, indicating the non-volatile memory operation.generated, metal atoms are exposed to chemisorb with hydro-gen atoms. At the ambient condition, hydrogen atoms can beadsorbed with oxygen atoms, configuring the hydroxy group (O-H) (Figure S4, Supporting Information). Moreover, the nano-grain distribution has been statistically analyzed with RF plasmapower variation. As the higher photo-induced force correspondsto the grain boundary of nano-grain (red area), lower photo-induced force designates the vdW lattice (blue) (Figure 2e). Sta-tistically extracting the nano-grain distribution, nano-grain areadistributed as 107.29 nm2 (300 W), 179.96 nm2 (350 W), and752.12 nm2 (400 W). Also, nano-grain length has been extractedas 16.09 nm (300 W), 18.54 nm (350 W), and 34.57 nm (400 W)(Figure 5).2.3. Evaluation of Bipolar Resistive Switching PerformanceTo evaluate the performance of resistivememory, cyclic I–V curvehas been measured (Figure 3a). Regarding the vdW 2D/3D het-erostructures, nano-crystallized vdW lattice corresponds to the“resistor”, while the bulk vdW lattice operated as “selector”. Thus,the monolithically-integrated nano-crystallized VSe2 /bulk VSe2Adv. Sci. 2025, 12, e10961 e10961 (6 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comFigure 5. Monolithic control of 1S1R memory cell device function. a) Evaluation of hysteresis characteristics in 1S1R memory cell. Modulating the1S (selector)/1R (resistive memory) ratio, the corresponding hysteresis window has been measured as 0.21 V, 1.64 V, and 2.51 V. b) Band alignmentof monolithically-integrated vdW 2D/3D heterostructure. c) Gate-tunable dI/dV cascade mapping with selector layer control (3, 5, and 7 layers). Apronounced DOS suppression region (electronic bandgap) is observed near zero bias in all cases, with the width of this gap systematically increasingwith selector dominance and gate bias modulation. d) Circuit symbol of 1S1R memory, indicating the dominant element of each 1S (selector)/1R(resistive memory) ratio.heterostructure derives the 1S1R cell characteristics. Combin-ing the selector (nano-crystallized VSe2) and resistor (bulk VSe2),memory state can be activated with threshold voltage Vth, whichcorresponds to the selector device operation. While the Imax, Imin,and IHRS have been measured as 6.91 × 10−10 A, 1.30 × 10−13 A,and 1.27 × 10−10 A (Figure 3b). Based on these current values,selectivity (Imax/IHRS) and on/off ratio (Imax/Imin) can be calcu-lated as 5.44 × 100 and 5.61 × 103 (Figure 3c,d). Both in posi-tive bias and negative bias range, the typical hysteresis loop hasbeen symmetrically observed with bipolar switching as state [0,S1], state [1, S3], state [0′, S4], and state [1′, S6]. HRS switchedto the LRS within a positive electric field (S1, E↑) at thresh-old voltage (Vth, S1) of +4 .80 V. LRS can be switched back toHRS by decreasing the positive electric field (S3, E↑) at Vth, S3of +3.20V, resulting the 1.6 V of hysteresis window. Reversely,LRS was switched to HRS with in negative electric field (S4,E↓) at Vth, S4 of −4.10V, and then switched back to LRS by de-creased negative electric field (S6, E↓) withinVth, S6 as−2.70 V, ex-hibiting symmetrical hysteresis window (1.60 V).Moreover, time-resolved current can be analyzed within sequential bias pulseAdv. Sci. 2025, 12, e10961 e10961 (7 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comconfiguration (S1–S6) (Figure 3e). Selecting the bias value be-tween the Vth, S1 – Vth, S3 and Vth, S4 – Vth, S6, current poses bipo-lar states (HRS [state “0”]/ LRS [state “1”]) for each bias value.Bipolar switching behavior are derived with possible combina-tion of LRS /HRS alignment with electrical field, which is con-figured with E↑, HRS (state [0, S1]), E↓P↑ (state [0′, S4]), E↑, LRS(state [1, S3]) and E↓, HRS (state [1′, S6]). Also, statical evalu-tation of HRS/LRS has been conducted in Figure 3f. HRS/LRSstate has been with switched with Vreset (-2.5 V), Vset (+7.5 V)and Vread (+4.0 V). Current value statically measured as 0.137 nAin HRS [state “0”] (Vreset (-2.5 V)→Vread (+4.0 V)), 0.851 nA inLRS [state “1”] (Vset (+7.5 V) →Vread (+4.0 V)), and 0.132 nA inHRS [state “0”] (Vreset (-2.5 V)→Vread (+4.0 V)). Thus, the practi-cal 1S1R application has been comprehensively validated withinvdW 2D/3D heterostructures, which can be utilized as veraatileadvances for M3D integration and its corresponding vdW deviceapplications.2.4. Spatial-Resolved Resistive Switching Mechanism via C-AFMMeasurementsAs depicted in Figure 4a,b, the C-AFM system has been com-bined with a dual-tip architecture with independently controlledbiasing and probing electrodes. By decoupling voltage applica-tion from current detection, this configuration enables real-time,spatially and temporally resolved imaging of resistive-switchingdynamics at the nanometer scale. As shown in Figure 4c, bias-dependent topography image and pixel distribution has been spa-tially resolved with C-AFM (Figures S6 and S7, Supporting Infor-mation), resulting in the local conductive filaments activation. C-AFM scan has been conducted with sequential “read” and “write”operation, which has been constructed as [1] Vreset (−2.5 V)→ [2]Vread (+4.0 V) [Reading “0”]→ [3] Vset (+7.5 V)→ [4] Vread (+4.0 V)[Reading “1”] → [5] Vreset (−2.5 V)→ [6] Vread (+4.0 V) [Reading“0”]) (Figure S9, Supporting Information). Furthermore, sampleDC bias was sequentially configured with positive “set” bias andnegative “reset” bias to exclude the possibility of gradual dissipa-tion of residual conductive filaments. Within “set” state, conduc-tive filaments have been activated with positive bias, resulting inthe topographical variation and LRS. After scanning with “set”state, “reset” scanning has been conducted with −2.5 V bias. As“reset” scan image exhibits the absence of topographical varia-tion and conductance, blocking the activation of conductive fil-aments. When “set” bias has been sequentially increased with“reset” scan, topographical variation and conductance correlateswith the sample DC bias, retaining the spatial reproducibility ofconductive filaments. Within such bias configuration, spatially-resolved topography and derivative image directly correspondsto the topography expansion, activation of conductive filaments,and vertical ionicmigration (Figure S8, Supporting Information).To further validate the spatially-resolved resistive switching dy-namics, two-box switching method has been applied. First, pre-scan has been conducted with Vread (+4.0 V), which indicates theHRS [state “0”]. After Vread (+4.0 V) scan, LRS [state “1”] has beenobserved with Vset (+7.5 V) scan. As this resistive memory deviceoperates as non-volatile memory, LRS [state “1”] has been con-sistently obtained with Vset (+7.5 V). So, LRS/HRS has been con-currently observedwithC-AFM two-box switching, which directlycorresponds the bipolar resistive switching dynamics (Figure S9,Supporting Information).2.5. Monolithic Control of 1S1R Memory Cell Device FunctionTo enable the practical implementation of monolithically inte-grated 1S1R resistive memory architectures, the vertical ratio be-tween the 1S and 1R layers was precisely engineered throughmonolithic integration, as illustrated in Figure 5a. By modulat-ing the RF plasma power, the thickness ratio of the 1S/1R stackwas systematically controlled, resulting in corresponding varia-tions in the hysteresis window of the 1S1R device: 0.21 V for 3selector layers, 1.64 V for 5 layers, and 2.51 V for 7 layers, re-spectively (Figure 5b). To achieve an artificial 2D/3D heterostruc-ture, an Ar +H2S plasma treatment has been applied, where theplasma power was used to selectively induce nano-crystallizationin the top bulk vdW layers. Main key advantage of our top-downapproach is the ability to precisely control the number of sulfur-ized layers by tuning the RF plasma power. This allows artificialmanipulation of both material properties and device character-istics. In contrast, bottom-up methods such as epitaxial growthrequire high temperatures, template substrate, and typically suf-fer from low yield. Moreover, they lack precise control over thenumber of nano-crystallized layers, making them unsuitable forthe fabrication of integrated 1S1R cells where such control is crit-ical. In comparison, our top-down bulk vdW nano-crystallizationapproach can be performed at room temperature and ensuresuniform plasma treatment across the substrate. By seamlesslyforming heterogeneous 2D vdW layers on pre-existing 3D bulkvdW materials, artificial vdW 2D/3D heterostructure has beenextensively fabricated and modulated. By varying the RF plasmapower, the vertical thickness ratio between the 1S and 1R layers isfinely tuned, enabling the transition between selector-dominantand resistor-dominant device behaviors. The resulting nano-crystalline VSe2 seamlessly integrates with the underlying bulklattice and functions as an ovonic threshold switch (OTS). Whenthe applied voltage exceeds Vth, a conductive path forms withinthe nano-crystalline VSe2 via carrier injection and field-inducedtrap filling, resulting in an abrupt transition from HRS to theLRS. Thus, the in-situ integration of nano-crystalline VSe2 OTSon a bulk vdW-based ReRAM layer enables the realization of amonolithically fabricated 1S1R cell. To probe the electronic bandstructure of nano-crystallized VSe2/bulk VSe2 heterostructure,gate-dependent differential conductance (dI/dV) spectroscopyhas been investigated with 3-, 5-, and 7-layer selectors (Figure 5c).This systematic bandgap enlargement corresponds to the inter-layer hybridization within the distorted van der Waals lattice.While the overall conductance increases with gate voltage (con-sistent with electrostatic doping), the bandgap position remainsrelatively stable. Furthermore, minor asymmetries in the dI/dVspectra directly reflect the asymmetrical band bending owing tothe interfacial potential gradients. Such band gap variation ofnano-crystallized VSe2, which can be associated with enhancedion migration and filament formation. As a nano-crystallizedlattice indicates an enhanced band gap in a laterally distorteddomain, such nano-crystallization induces conductive filamentsto migrate through the grain boundary. While bulk VSe2 latticegenerates conductive filaments with the electroforming process,Adv. Sci. 2025, 12, e10961 e10961 (8 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comFigure 6. Synaptic response of monolithically-integrated vdW 1S1R memory function. a) Schematic illustration of the resistive switching mechanism invdW 2D/3D heterostructure, separating the HRS and LRS with a heterogeneous bandgap. b) Synaptic plasticity with LTP/LTD (±5 V Pulse, 100 pulses),and its c) temperature-dependent synaptic plasticity with 300–450 K variation (±5 V Pulse, 100 pulses). d) Statistical evaluation of device-to-devicereproducibility, device-to-device variation, and endurance (maximum cycles) of 50 devices. e) Synaptic behavior with heterogeneous pulse durations(2.5, 5.0, 7.5, and 10.0 s), pulse numbers (1, 3, 5, and 7), and pulse intensities (25, 50, 75, and 100 mV).resulting in a heterogeneous threshold voltage configuration(Figure 5d).2.6. Synaptic Response of Monolithically-Integrated 1S1RMemory Cell DeviceWhile bulk VSe2 lattice generates conductive filaments with theelectroforming process, resulting in a heterogeneous thresholdconfiguration. Cross-sectional schematic of the HRS and LRS in-dicates the resistive switching mechanism based on ion-assistedgrain boundary modulation, filament, ion dynamics, and grainboundary-induced conduction (Figure 6a). Robust long-term po-tentiation and depression (LTP/LTD) characteristics have beendemonstrated in our monolithically-integrated 1S1R device un-der repeated pulse stimulation, as shown in Figure 6b. Tempera-ture‑dependent measurements from 300K to 450K demonstrateLTP/LTD behavior up to 450K (Figure 6c). The linear increase inpost‑synaptic current with temperature reflects enhanced ionicmobility within the nano‑crystalline VSe2 selector, yet the ab-sence of abrupt conductance failures occurs, indicating the ther-mal robustness of the vdW 2D/3D heterostructure for stable neu-romorphic operation. All devices exhibit a clockwise I–V hystere-sis loop, indicative of bipolar switching governed by field‑inducedfilament growth and rupture stabilized by the nonlinear thresh-old behavior. For over 50 cells, the standard deviation of switchingvoltages and current levels remains below 5% (Figure 6d), con-firming the reproducible compliance control provided by the inte-Adv. Sci. 2025, 12, e10961 e10961 (9 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comgrated selector. Under ambient conditions, the monolithic 1S1Rcells sustain >1.8 × 107 switching cycles (Figure 6d). The deviceexhibited stable endurance characteristics up to ≈107 switchingcycles at both 300 K and 450 K, with negligible degradation inHRS/LRS values. The consistent resistance states across the en-tire cycling range confirm the robust operational stability of themonolithically integrated architecture (Figure S10, SupportingInformation). Modulating the electrical pulse parameters (num-ber, duration, intensity), the 1S1R cells exhibit a gradual con-ductance variation of analog synapses (Figure 6e–g). Owing tothe nano‑crystallization, decreased conductance of selector layerlimits abrupt current increment, enabling linear weight updatesacross multiple resistance states with minimal nonlinearity. Pre-viously, synaptic weight updates have been reported at the inter-faces of vdW heterostructures,[36] such synaptic behavior biolog-ically mimics weight adjustment and demonstrates neuromor-phic plasticity through controllable LTP/LTD pulse characteris-tics. Similarly, our artificial vdW 2D/3D heterostructure (nano-crystalline VSe2/bulk VSe2 interface) enables the synaptic func-tionality with interfacial charge accumulation at the vdW inter-face. C-AFM measurements revealed that increasing either thecontact area (400, 1225, and 2500 nm2) or the contact force (50,75, and 100 nN) led to the slight increase in LRS current (FigureS10, Supporting Information). This increment can be attributedto a reduced contact resistance arising from an enlarged devicecontact area, as well as an increased effective conductive cross-section or number of parallel conductive filaments within theactive layer. Furthermore, enhanced local pressure and associ-ated Joule heating further promote defect generation and migra-tion, facilitating filament growth and consequently lowering LRSresistance. These synergistic effects enable the area- and force-dependent LRS modulation behavior.3. ConclusionIn summary, a monolithically-integrated 1S1R cell has been pre-sented with vdW 2D/3D heterostructure, which addresses long-standing challenges in 3D vertical device integration technolo-gies. The synergistic incorporation of Ar + H2S plasma sulfu-rization induces nano-grain formation at the bulk VSe2, yield-ing stable bipolar resistive switching behavior. The monolithic-integrated 1S1R cell exhibits Imax, Imin, and IHRS as 6.91 × 10−10A, 1.30 × 10−13 A, 1.27 × 10−10 A, resulting in the low leakagecurrents, robust switching ratios, and reliable bipolar memorystates. As bipolar switching mechanism has been sequentiallyresolved with “read” and “write” operation, LRS/HRS has beenconcurrently observedwith two-box switching, which directly cor-responds the bipolar resistive switching dynamics. To achieve thepractical application of monolithically-integrated resistive mem-ory, the ratio of 1S (selector)/1R (resistive memory) has beenmonolithically controlled. Moreover, synaptic behavior has beenvalidated in monolithically-integrated 1S1R device with repeatedLTP/LTD pulse stimulation, resulting the gradual conductancevariation of analog synapses, while sustaining the standard de-viation of switching voltages and current levels remains as 5%and maximum switching cycles as 1.8 × 107 switching. In con-clusion, we envision that our monolithically-integrated 1S1R cellcan offer a generalizable platform for next-generation 3D inte-grated neuromorphic device and AI hardware.4. Experimental SectionMechanical Exfoliation and Transfer of vdW VSe2: Before mechanicalexfoliation and dry transfer, a polydimethylsiloxane stamp was attachedto a glass cover. vdW VSe2 were mechanically exfoliated from bulk crystals(HQGraphene, Netherlands) onto polydimethylsiloxane stamps and thentransferred onto the substrate by applying a transfer condition of 70 °C.vdW 2D/3D Heterostructures Fabrication for Monolithically-Integrtated1S1R Cell: In vdW 2D/3D heterostructures, the nano-crystallized vdWlattice functions as the resistive element, while the bulk vdW lattice servesas the selector, enabling monolithically-integrated 1S1R configurations. Toinduce nano-crystallization of VSe2, inductively coupled plasma-enhancedchemical vapor deposition (ICP-PECVD, AFS-IC6T, Korea) was employed.Prior to plasma treatment, the chamber was evacuated to a high vacuum(≈10−5 Torr) to eliminate contaminants and suppress undesired reactionsduring synthesis. The RF plasma power was maintained at 400 W, withconstant gas flow conditions of Ar and H2S (50 sccm each) at 25 mTorrpressure and room temperature, ensuring fabrication of vdW 2D/3D het-erostructures.AFM Measurements: AFM (NX-10 AFM, Park Systems, Republic ofKorea) measurements were conducted with an Electri-Multi75G can-tilever. A silver paste electrode (Elcoat P-100, CANS, Japan) was selec-tively deposited on the sample edge to induce electrical contact. TheElectriMulti75-G cantilever was calibrated with a tip radius of 25 nm, alength of 225 μm, a height of 17 μm, a width of 28 μm, and a spring con-stant of 3.3 Nm−1, resulting in a resonance frequency of 60.8 kHz. C-AFMmeasurements with a continuous voltage waveform, which was configuredwith 8 s for one cycle (3 cycle measurements), and sample bias range as−10 –+10 V (Vmax as +10 V/ Vmin as −10 V). Current-voltage characteris-tics through the sulfurized vdW materials were probed within the CAFMprobe (Electri-Multi75G, tip radius as 25 nm) to operate as the top elec-trode of the vdW materials, grounded to the Au substrate. In addition,PiFM (NX-IR, Park Systems, Republic of Korea) with a PPP-NCHR can-tilever was employed for the PiFMmeasurements. The QCL laser used forPiFMwas adjusted to an intensity of 1%. Prior to the PiFMmeasurements,the QCL laser was focused on the initial spatial intensity positions directlyunder the AFM tip. Customized vdW SPM device set-up was installed withMibot (IMINA, Switzerland) and AFM (NX 10, Park Systems, South Korea)with Tungsten probe (PT-010N-15-B8) with 10 nm tip radius, 15 mm inlength), enabling the electrical pulse measurements and I–V curve sweep(Bias range −170 V–170 V, 60 Hz, AC ±107 V).Material Characterization: XPS measurements (XIS Supra+, Kratos,United Kingdom) were used to characterize vdW materials, with an X-rayspot size of 400 μm. Peak deconvolution was performed with the profilesaligned using the C 1s peak at 285 eV. The XPS data were calibrated us-ing the CASAXPS software (version 8.1). Optical microscopy (U-MSSP4,Olympus, Japan) and FE-SEM (S-4800, Hitachi, Japan) were used to exam-ine the transferred flakes. For cross-sectional TEM specimen preparation,a focused ion beam instrument (NX2000, Hitachi Ltd., Japan) was used,employing a Ga+ ion beam (30–5 keV) and a lift-off process to etch thespecimens. TEM (JEM-2100F, JEOL, Japan) and XRD (Empyrean, MalvernPANalytical, United Kingdom) were used to observe the lattice structure,EDS, and SAED patterns of the sulfurized VSe2 structures at the atomicscale.Supporting InformationSupporting Information is available from the Wiley Online Library or fromthe author.AcknowledgementsThis research was supported by the Basic Science Research Program of theNational Research Foundation of Korea (NRF) funded by the Ministry ofEducation (No. 2022R1A3B1078163). This study was supported by the In-stitute for Basic Science (grant number IBS-R027-D1). This work was sup-ported by the Korean Collaborative & High-tech Initiative for ProspectiveAdv. Sci. 2025, 12, e10961 e10961 (10 of 12) © 2025 The Author(s). Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.comwww.advancedsciencenews.com www.advancedscience.comSemiconductor Research (K-CHIPS) (20024772), funded by the Ministryof Trade, Industry & Energy (MOTIE, Korea). This study was supportedby the MOTIE (Ministry of Trade, Industry, and Energy (grant number1415187508) for the development of future semiconductor devices. Thisstudy was supported by the National Research Foundation (NRF) fundedby the Korean government (MSIT) (No. RS-2024-00437142). This workwas supported by the Technology Innovation Program (20017367, De-velopment of precise manufacturing technology for CMP pad condition-ers), funded By the Ministry of Trade, Industry & Energy (MOTIE, Korea).This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government (MSIT)(RS-2024-00437142).This work was supported by the Technology Innovation Program (or In-dustrial Strategic Technology Development Program) (RS-2023-00235156,Development of materials and process technologies for next-generationchemical-mechanical polishing including eddy current sensor and highsensitivity pressure sensor) funded by the Ministry of Trade, industry &Energy (MOTIE, Korea) (1415187584).Conflict of InterestThe authors declare no conflict of interest.Author ContributionsJ.L., G.K., H.S., and S.H. contributed equally to this work. J.L., G.K., H.S.,and S.H. prepared samples and performed experiments. G.K., H.C., H.K.,S.S., S.S., H.L., C.P., H.S., H.H., G.B., H.S., D.C., and D.L. performed thetechnical discussions on resistive switching mechanism. Y.C., G.H., G.J.,and Y.L. provided technical advice on the PiFM systems. T.T. and K.W. pro-vide the bulk hexagonal boron nitride samples. M.G. and A.B. include inRaman spectroscopy measurements. Y.K., S.K., and S.B. included in thetechnical discussions about artificial 2D/3D heterostructure. A.O., Y.K.,and L.F., A.H., W.J., J.L., G.K., H.S., and S.H. wrote the manuscript withcontributions from all the authors. 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Advanced Science published by Wiley-VCH GmbH 21983844, 2025, 43, Downloaded from https://advanced.onlinelibrary.wiley.com/doi/10.1002/advs.202510961 by National Institute For, Wiley Online Library on [20/11/2025]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons Licensehttp://www.advancedsciencenews.comhttp://www.advancedscience.com Monolithically-Integrated van der Waals Synaptic Memory via Bulk Nano-Crystallization 1. Introduction 2. Results and Discussion 2.1. Monolithically-Integrated 1S1R Cell in vdW 2D/3D Heterostructure 2.2. Atomic-Scale Observation of Monolithically-Integrated vdW 2D/3D Heterostructure 2.3. Evaluation of Bipolar Resistive Switching Performance 2.4. Spatial-Resolved Resistive Switching Mechanism via C-AFM Measurements 2.5. Monolithic Control of 1S1R Memory Cell Device Function 2.6. Synaptic Response of Monolithically-Integrated 1S1R Memory Cell Device 3. Conclusion 4. Experimental Section Supporting Information Acknowledgements Conflict of Interest Author Contributions Data Availability Statement Keywords