# Fileset

[Suppl_Info_v7.6.pdf](https://mdr.nims.go.jp/filesets/695b3783-00d4-4ba2-8d5b-8c5d35e61b09/download)

## Creator

Joaquin Santandera, Iñigo Martin-Fernandez, Carlos Carbonell, Alex Rodríguez-Iglesias, Laura Fuentes-Rodríguez, Marta Fernández-Regúlez, Llibertat Abad, Aitor F. Lopeandia, Arindom Chatterjee, Nini Pryds, Luis Fonseca, Marc Salleras

## Rights

[Creative Commons BY Attribution 4.0 International](https://creativecommons.org/licenses/by/4.0/)

## Other metadata

[A novel approach to micro-fabricated thermoelectric generators with SrTiO3](https://mdr.nims.go.jp/datasets/b0c3b140-3c57-4a13-aeac-fc9419664796)

## Fulltext

Microsoft Word - Suppl_Info_v7.6.docx  Supplementary Information A novel approach to micro-fabricated thermoelectric generators with SrTiO3 Joaquin Santandera, Iñigo Martin-Fernandeza, Carlos Carbonella, Alex Rodríguez-Iglesiasa, Laura Fuentes-Rodrígueza, Marta Fernández-Regúleza, Llibertat Abada, Aitor F. Lopeandiab,c, Arindom Chatterjeed, Nini Prydsd, Luis Fonsecaa, and Marc Sallerasa* aInstitute of Microelectronics of Barcelona (IMB-CNM-CSIC), 08193 Bellaterra, Spain. bPhysics Department, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain. cGTNAM at Institut Català de Nanociència i Nanotecnologia (ICN2), 08193 Bellaterra, Spain. dDepartment of Energy Conversion and Storage, Technical University of Denmark, 2800 Kgs Lyngby, Denmark. *marc.salleras@csic.es     Figure S1: Schematics of the fabrication scheme. The fabrication is divided in 2 blocks. Block 1 comprises the process steps at a wafer-scale level. Block 2 comprises the process steps at a chip-scale level. (1) Starting wafers; (2) Selective doping of Si with BBr3; (3) Growth of 100 nm SiO2 by thermal oxidation (4) deposition of low stress Si3N4 by LPCVD; (5) Optical lithography followed by RIE and photoresist removal to pattern the membrane windows; (6) Partial wet etch with KOH of the Si and wafer dicing into chips; (7) PLD deposition of the Nb:STO; (8) Optical lithography followed by Ar plasma and photoresist removal to pattern the Nb:STO; (9) PECVD deposition of 200 nm SiO2 as interlevel oxide; (10) Optical lithography, wet etching, and photoresist removal to define the bias to the Nb:STO; (11) Optical lithography, evaporation of 10 nm Ti and 200 nm W and lift-off to pattern the current collectors and the heaters, the tracks and the metal pads; and (12) Complete KOH etching of the Si to define the membranes.      Figure S2. Test structures used for the measurement of electrical parameters. The chips include a set of electrical test structures able to measure basic electrical tech-nological parameters like the sheet resistance of conducting layers (Van der Pauw test structures, lower left image in Figure S2) and the contact resistance between conducting layers (Kelvin test structure, lower right image in Figure S2). Table S1 summarizes the obtained values, which confirm that the chips were fabricated as expected. The value of the sheet resistance of the Nb:STO permits the calculation of the electrical conductance provided the thickness of the layer (149 nm).     Table S1. Measurements obtained for the technological parameters: sheet resistances of the metal and of the Nb:STO layers and contact resistance between the metal and the Nb:STO layers in a 20 x 20 µm2 contact area. R□ metal 1.3 Ω/□ R□ Nb:STO 49 kΩ/□ Rc metal to Nb:STO 1.7 kΩ     Figure S3. Determination of the Seebeck coefficient (S) for each of the five devices from the slope of the VOC vs ΔT curves. The average is S = -135.7 ± 8.4 μV·K-1.      Figure S4. Determination of the thermal conductance (K) of the five devices from the slope of the ΔT vs heater power curves.      Figure S5: Simplified thermal model of the µTEG. In the calculation of the thermal conductance of the TEG (KTEG) the simple thermal model in Figure S5 is used. In this model the node Tcold is where the heater/thermometer is placed and Thot is the hotplate. KTEG is the thermal conductance of the device (the thermoelectric membrane), KLK is the leakage thermal conductance (through parasitic heat-flow paths), and KS is the thermal conductance from the heater/thermometer towards the ambient. For this discussion, we will focus on D4 device and will ignore the KLK term as it is expected to be much smaller than KTEG. From our test mode results, we can calculate the thermal conductance from the slope of ΔT vs heater power curves (Figure S4) resulting in KD4 = 94.48·μW·K-1. According to the thermal model, this thermal conductance corre-sponds to the parallel connection of KTEG and KS, therefore KD4 = KTEG,D4 + KS,D4. In harvest mode we set the hotplate temperature at 175 ºC, and the heater (used as a ther-mometer) measures a temperature of 151 ºC, while the ambient temperature measured is 25 ºC. Then we can calculate for D4: 𝑄=𝑑𝑇 · 𝐾 → 𝑄=(175-151 ℃) · 𝐾 = (151-25  ℃) · 𝐾  24  ℃ · 𝐾 = 126  ℃ · 𝐾 → 𝐾 = 126 24⁄ · 𝐾 = 5.25 · 𝐾   And using:    𝐾 +𝐾 =94.48 ·  μ𝑊 · 𝐾  We can obtain:   𝐾 =79.37 · μ𝑊 · 𝐾 → 𝐾 =15.12 · μ𝑊 · 𝐾  The KTEG value obtained can be used to calculate a ZT value.