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[Juhyung Seo](https://orcid.org/0000-0003-4396-9439), Jihyun Shin, Ulrike Kraft, [Hocheon Yoo](https://orcid.org/0000-0003-0772-3327), [Ryoma Hayakawa](https://orcid.org/0000-0002-1442-8230), [Yutaka Wakayama](https://orcid.org/0000-0002-0801-8884)

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[Dielectric-Stack-Engineered Anti-Ambipolar Transistors for Low-Voltage Ternary Logic](https://mdr.nims.go.jp/datasets/4954bda7-6e9f-4b78-9324-5f915f1e2466)

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Dielectric-Stack-Engineered Anti-Ambipolar Transistors for Low-Voltage Ternary Logic  Received 9 September 2026; accepted 21 September 2026. Date of publication 6 October 2026; date of current version 15 October 2026. The review of this article was arranged by Editor S. Menzel. Digital Object Identifier 10.1109/JEDS.2026.3737142 Dielectric-Stack-Engineered Anti-Ambipolar Transistors for Low-Voltage Ternary Logic JUHYUNG SEO 1,2 (Member, IEEE), JIHYUN SHIN2,3, ULRIKE KRAFT3, HOCHEON YOO 1,4 (Member, IEEE), RYOMA HAYAKAWA2, AND YUTAKA WAKAYAMA2 1Department of Electronic Engineering, Hanyang University, Seoul 04763, Republic of Korea 2Research Center for Materials Nanoarchitectonics (MANA), National Institute for Materials Science (NIMS), Tsukuba 305-0044, Japan 3Organic Bioelectronics Research Group, Max Planck Institute for Polymer Research, 55128 Mainz, Germany 4Department of Artificial Intelligence Semiconductor Engineering, Hanyang University, Seoul 04763, Republic of Korea CORRESPONDING AUTHORS: H. YOO (hocheon@hanyang.ac.kr), R. HAYAKAWA (HAYAKAWA.Ryoma@nims.go.jp), AND Y. WAKAYAMA (wakayama.yutaka@nims.go.jp) This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by Korean Government \[Ministry of Science and ICT (MSIT)\] under Grant RS-2024-00438999, Grant RS-2026-25493157, and Grant RS-2026-25540048; in part by Korea Basic Science Institute (National Research Facilities and Equipment Center) grant funded by Korean Government (MSIT) under Grant RS-2025-00558813; in part by the Japan Society for the Promotion of Science (JSPS) KAKENHI under Grant 23H00269; in part by the Canon Foundation; in part by the Innovative Science and Technology Initiative for Security, Acquisition, Technology and Logistics Agency (ATLA) under Grant JPJ004596; in part by the Electronics and Telecommunications Research Institute (ETRI) grant funded by Korean Government, Neuromorphic Computing, Synaptic Device, Neuron Device, Activation function, Vertical Stacking, under Grant 4011-2026-00002; and in part by the Korea Industrial Technology Association (KOITA) under Grant KOITA-2026-017. ABSTRACT We demonstrate an ultralow-voltage ternary multi-valued logic (MVL) inverter based on an extended p-channel anti-ambipolar transistor (Ep-AAT) employing an optimized HfO2/polystyrene gate dielectric stack. The HfO2 dielectric enables low-voltage operation, while the polystyrene surface layer provides a low-surface-energy interface for stable organic channel formation. The Ep-AAT exhibits an intrinsic N-shaped transfer characteristic with a clear negative transconductance region, explained by the combined contributions of the N1, P1, and P2 channels. Integrated with an n-type transistor, the Ep- AAT realizes a ternary MVL inverter with three distinct logic states at a supply voltage of 2 V without additional circuit complexity. These results highlight the potential of HfO2/polystyrene-based Ep-AATs for MVL circuits. INDEX TERMS Anti-ambipolar transistor, negative transconductance, ternary multi-valued logic, ultralow- voltage inverter, high-k gate dielectric. I. INTRODUCTION As energy efficiency has become a primary constraint in modern computing systems, multi-valued logic (MVL) has gained attention as an alternative to conventional binary logic \[1\], \[2\]. Ternary logic has the potential to reduce circuit complexity and switching operations by increasing information density. However, existing implementations often rely on circuit overhead such as multiple transistors, resis- tive networks, or precise voltage division schemes \[3\], \[4\]. Thus, device-level approaches that generate ternary outputs are highly desirable. Recently, anti-ambipolar transistors (AATs) exhibiting nonlinear N-shaped transfer characteristics with negative transconductance (NTC) have been used for MVL. Yet, conventional devices still require high operating voltages \[5\]. In this work, we propose an organic semiconductor-based extended p-channel anti-ambipolar transistor (Ep-AAT) inte- grated with an optimized dielectric stack. A fully extended p-channel architecture is combined with a high-k HfO2 gate dielectric and a polystyrene (PS) surface layer to enable low-voltage operation. HfO2 dielectric reduces the operat- ing voltage, while PS optimizes the interface for uniform channel formation. Unlike conventional AATs, the Ep-AAT forms an N-shaped transfer characteristic and NTC region through the interplay of the N1, P1 and P2 channels, driven by the competition between electron and hole transport. © 2026 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ VOLUME 14, 2026 875[https://orcid.org/0000-0003-4396-9439](https://orcid.org/0000-0003-4396-9439)[https://orcid.org/0000-0003-0772-3327](https://orcid.org/0000-0003-0772-3327)SEO et al.: DIELECTRIC-STACK-ENGINEERED AATs FOR LOW-VOLTAGE TERNARY LOGIC TABLE 1. Comparison of ternary MVL inverters based on AAT-type devices. By integrating the Ep-AAT with an n-type transistor, we demonstrate ternary MVL inverter operation at a supply voltage of 2 V, without additional circuit complexity. The ternary-state formation mechanism is systematically ana- lyzed based on the transfer characteristics of the constituent devices. II. FABRICATION AND MEASUREMENT We fabricated an ultralow-voltage ternary inverter consisting of an Ep-AAT and a single n-type thin-film transistor (TFT). The Ep-AAT devices were fabricated on SiO2 (300 nm)/Si substrates with thermally evaporated Cr/Au gate electrodes (5/30 nm). A 15 nm thick HfO2 gate dielectric was deposited by atomic layer deposition (ALD), followed by a 5 nm spin-coated PS layer. Prior to the PS deposition, the HfO2 surface was treated with UV-ozone for 15 min to improve the surface wettability. The 5 nm-thick PS layer (Sigma- Aldrich, 182427) was then formed by spin-coating a 0.2 wt% solution in toluene at 6,000 rpm for 60 s. The film was subsequently annealed at 100 ◦C for 1 h under vacuum to remove the residual solvent. The resulting PS surface exhibited a smooth morphology with a root-mean-square (RMS) roughness of about 0.2 nm, as confirmed by atomic force microscopy, providing a uniform surface for the subsequent growth of the organic semiconductor layers. The n-type PhC2H4-benzo\[de\]isoquinolino\[1,8- gh\]quinolone diimide (PhC2-BQQDI) and p-type 2,7-dioctyl \[1\]benzothieno-\[3,2-b\] \[1\]benzothiophene (C8-BTBT) organic semiconductors layers were thermally evaporated to thicknesses of 30 and 20 nm, respectively, followed by top Au electrodes (30 nm). All channels and electrodes were patterned using shadow masks, with channel lengths of 80 µm for the Ep-AAT and 40 µm for the n-type TFT, enabling their direct interconnection and seamless formation of the inverter architecture in a single fabrication step. III. RESULTS We demonstrate a low-voltage Ep-AAT employing a PS/HfO2 gate dielectric stack for MVL circuit applications. The high dielectric constant of HfO2 (k ≈ 20-25) enables low-voltage operation with reduced gate leakage \[6\]. In addi- tion, the PS surface layer provides a hydrophobic interface for organic semiconductor deposition and stable channel FIGURE 1. (a) Optical microscopy image and (b) schematic diagram of the HfO2-based Ep-AAT heterojunction device. Transfer characteristics, including drain current (IDS) and gate current (IGS), of single TFTs based on (c) p-type C8-BTBT and (d) n-type PhC2-BQQDI. (e) Transfer characteristics of the Ep-AAT device with a PS/HfO2 gate dielectric, exhibiting an N-shaped curve. (f) Corresponding gm characteristics and linear-scale transfer curve (inset). formation by modifying the HfO2 surface energy \[5\]. Fig. 1a and Fig. 1b show an optical microscopy image and a schematic diagram of the PS/HfO2-based device, respec- tively. Unlike conventional AATs that exhibit a Λ-shaped transfer curve, the Ep-AAT adopts a fully extended p-channel architecture in which heterojunctions are formed between the n-type channel (N1) and the p-type channels (P1 and 876 VOLUME 14, 2026SEO et al.: DIELECTRIC-STACK-ENGINEERED AATs FOR LOW-VOLTAGE TERNARY LOGIC FIGURE 2. (a) Device schematics and transfer characteristics of Ep-AAT. (b) Decomposition of the N-shaped transfer curve in Ep-AAT into N1, P1, and P2 contributions, explaining peak and valley formation with NTC effects. (c) Transfer characteristics of the Ep-AAT under different VDS conditions (−2 and −3 V). P2) along the source-drain direction. Here, P1 denotes the bottom p-type channel, whereas P2 denotes the upper p-type channel deposited on N1. The transfer characteristics of the individual organic transistors were first evaluated, as shown in Fig. 1c and Fig. 1d. The p- and n-type TFTs exhibited stable transfer behavior at drain-source voltage (VDS) = −2 and 2 V, respectively, over the corresponding gate-source voltage (VGS) ranges. The turn-on voltage (VT) of the n-type TFT, denoted as VT N1, was extracted to be approximately +0.4 V (Fig. 1d). Next, the transfer characteristics of the Ep-AAT device were measured. As shown in Fig. 1e, the device exhibits an N-shaped transfer characteristic with NTC behavior during the p-channel gate-bias sweep at VDS = −2 V. The peak current appears near VGS ≈ −1.35 V, originating from the overlapping conduction of the N1 and P1 channels (N1 ∩ P1) (Fig. 2a,b). Since N1 exchanges electrons with the drain electrode, the gate voltage effectively applied to N1 is VGS− VDS, so that N1 remains in the accumulation state at VGS ≈ −1.35 V (VGS− VDS = +0.65 V \> VT N1), whereas P1 is controlled by the global VGS with respect to the grounded source. With further gate bias, the drain current decreases and then increases again at more negative gate voltages (VGS \< −2 V) due to P2 activation. The VT of the P2 (VT P2) is shifted more negatively than that of P1 because the gate field must pass through the underlying N1 layer. While N1 is in accumulation, the accumulated electrons screen the gate field from P2. Once a depletion layer forms in N1, the gate field penetrates to P2, and the resulting potential redistribution across the stack makes the hole accumulation in P2 occur at a more negative VGS. As a result, the valley region appears between the cutoff of N1 and the onset of P2 conduction, and the overall transfer characteristic can be expressed as (N1 ∩ P1) ∪ P2. Fig. 1f shows the corresponding characteristics in the transconductance (gm) domain. The gm curve peaks near VGS ≈ −1.35 V and reaches a minimum of −0.11 µS at the valley. A slight hysteresis observed along the falling and re-increasing regions around the valley (Fig. 1e) is attributed to weak interfacial traps between the N1 and P2 channels \[5\], \[12\], \[13\], as the gate dielectric interface is effectively passivated by the PS FIGURE 3. (a) Transfer characteristics of Ep-AAT devices with SiO2, parylene, and HfO2 gate dielectrics. (b–d) Comparison of SiO2-, parylene-, and PS/HfO2-based Ep-AAT devices: (b) VDS bias conditions and extracted Vvalley, Vpeak, and VT, (c) Ci and \|Vpeak \|, and (d) SS and capacitive switching energy. layer \[14\], \[15\], \[16\]. This hysteresis appears selectively in the region where the P2 conduction sets in, consistent with the N1/P2 heterointerface origin. It is well established that bare high-k oxide dielectrics such as HfO2 and AlOx induce pronounced hysteresis in organic TFTs owing to trap states at and near the oxide surface \[17\], and that thin interlayers such as self-assembled monolayers or poly- mer films effectively shield the organic channel from these traps \[18\], \[19\]. Consistent with these reports, the forward and reverse sweeps of the PS-treated HfO2 device nearly coincide except for the weak N1/P2 contribution described above (Fig. 1e). To investigate the effect of dielectric-stack engineering on NTC operation, Ep-AAT devices were fabricated with two reference dielectric configurations, a 15 nm parylene-treated SiO2 (300 nm)/Si substrates and a local-gate structure with a 500 nm parylene gate dielectric. As shown in Fig. 3a, both devices exhibit typical N-shaped transfer characteristics but require a high VGS of about −50 V because of the large dielectric thickness and low dielectric constant, limiting low-voltage MVL operation. Fig. 3b compares the voltage ranges of the two transition regions, from VT to the peak current voltage (Vpeak) and from Vpeak to the valley current voltage (Vvalley). In the optimized Ep-AAT device, these ranges are reduced by up to 97.4% and 97.1%, respectively, demonstrating effective voltage scaling enabled by the high-k dielectric and interfacial surface modification. Fig. 3c shows the gate-dielectric capacitance per unit area (Ci) and \|Vpeak\| as a function of the gate dielectric. The PS/HfO2-based VOLUME 14, 2026 877SEO et al.: DIELECTRIC-STACK-ENGINEERED AATs FOR LOW-VOLTAGE TERNARY LOGIC device exhibits a Ci of 330 nF·cm−2, more than a 200-fold enhancement, greatly reducing the voltage required to reach the peak current. Based on these transfer characteristics and gate capacitance values, the subthreshold swing (SS) and capacitive switching energy of the Ep-AAT devices were compared (Fig. 3d). The capacitive switching energy was estimated from the energy stored in the gate capacitor during a voltage transition and calculated using Equation (1) \[20\], \[21\], Capacitive S witching Energy = 1 2 CiWL(∆V)2 (1) where W is the channel width, L is the channel length, and ∆V is the voltage swing between Vpeak and Vvalley. For the SiO2- and parylene-based Ep-AAT devices, W and L were 1000 µm and 100 µm, respectively. For the HfO2-based Ep-AAT device, W and L were 60 µm and 80 µm, respec- tively. The SS was extracted using Equation (2) \[22\], S S = �  dlog(ID) d(VGS ) �−1 (2) where VGS is the VGS and IDS is the drain current. Despite its larger Ci, the PS/HfO2-based device achieves orders-of- magnitude lower switching energy owing to the reduced operating voltage and much smaller SS. To further elucidate the drain-bias dependence of the NTC characteristics, the operation of the Ep-AAT is analyzed in terms of the electrode-referenced channel configuration (Fig. 2a,b). Because the N1 channel exchanges electrons with the drain terminal, the biased drain acts as an effective source for N1, defining the effective VGS applied to the N1 channel as VGS,eff = VGS− VDS. Electron accumulation in the N1 channel occurs when VGS,eff exceeds VT N1, and the accumulation condition (VGS \> VT N1+ VDS) therefore translates along the VGS axis by VDS. At VDS = −2 V, as VGS is swept from 0 V to −2 V, VGS,eff decreases from + 2 V to 0 V, and the N1 channel is cut off at VGS = VT N1 − 2 V, at which point the drain current begins to decrease. The valley is subsequently formed at the onset of P2 conduction. When \|VDS\| increases to 3 V, VGS,eff remains above VT N1 over the same VGS range, and the cutoff point and the resulting valley are extended toward more negative gate voltages, to around VGS = VT N1 − 3 V. Furthermore, since the entire N1 characteristic translates along the VGS axis by VDS, the intersection between the N1 and P1 curves, which defines Vpeak, also shifts partially toward more negative VGS. The VDS dependence was experimentally verified by mea- suring the identical Ep-AAT device at VDS = −2 and −3 V, which correspond to the supply voltages of the ternary inverter (Fig. 2c). As \|VDS\| increases from 2 V to 3 V, Vvalley shifts from −2.35 V to −3.05 V, following the translation of the N1 cutoff point by VDS, whereas Vpeak shifts only from −1.50 V to −1.75 V, as expected from its origin at the intersection of the N1 and P1 curves. In addition, Ipeak and Ivalley increase from 5.5 × 10−8 A to 2.0 × 10−7 A and from 5.7 × 10−9 A to 4.2 × 10−8 A, respectively, owing to FIGURE 4. (a) Circuit schematic of the ultralow-voltage ternary MVL inverter. (b) Voltage transfer characteristics of the ternary inverter, showing three distinct logic states (‘‘1’’, ‘‘1/2’’, and ‘‘0’’). (c) Matched transfer characteristics of the Ep-AAT and the n-type TFT on a logarithmic scale. (d) Voltage gain characteristics of the ternary inverter. the larger drain bias. These results confirm that the drain bias systematically modulates the NTC characteristics in accordance with the effective-source analysis. Furthermore, the fabricated device was integrated into a ternary MVL inverter. Fig. 4a shows the inverter con- figuration composed of a PS/HfO2-based Ep-AAT and an n-type transistor, where VIN is applied to both device gates and VOUT is measured at the common node. As shown in Fig. 4b, the voltage transfer characteristics (VTCs) clearly resolve three logic states, “1”, “1/2”, and “0”, even at low operating voltage (VDD = 2 V). The operating mechanism is explained by the matched transfer curves of the Ep-AAT and the n-type TFT shown on a logarithmic scale in Fig. 4c. At low VIN (range i), the VGS of the n-type TFT is below its VT (VT N1), while the VGS of the Ep-AAT approaches its Vvalley. Under this condition, the Ep-AAT dominates the circuit current, delivering VDD to the output and yielding logic state “1”. With increasing VIN toward Vpeak, the n-type TFT begins to conduct. At the same time, the current of the Ep-AAT also increases. As a result, both devices contribute significantly to the output current, leading to voltage division and the intermediate logic state “1/2” in the intermediate VIN region (range ii) of 0.5-0.75 V. Upon further increasing VIN, the two transfer characteristics reach their intersection, beyond which the current of the n-type TFT exceeds that of the Ep-AAT. This ultimately leads to the transition toward logic state “0” in range iii, as the n-type TFT becomes dominant and pulls the VOUT toward ground while the Ep- AAT is turned off. Although the relationship between the intersection point and the intermediate logic state observed in conventional CMOS inverters does not directly apply to our 878 VOLUME 14, 2026SEO et al.: DIELECTRIC-STACK-ENGINEERED AATs FOR LOW-VOLTAGE TERNARY LOGIC FIGURE 5. Statistical analysis of Ep-AAT devices and ternary inverters. (a) Average values of the VT, Vpeak, and Vvalley extracted from the transfer curves of the twenty Ep-AAT devices. (b) Average values of Ipeak, Ivalley, and Imax. (c) Overlaid VTC curves of the twenty ternary inverters measured at VDD = 2 V, exhibiting three distinct logic states (‘‘1’’, ‘‘1/2’’, and ‘‘0’’) in all devices. The inset shows a schematic illustration of the ternary inverter configuration. (d) Average voltage gains of the first and second transitions extracted from the twenty VTCs. (e) Histograms of the two transition voltages with the corresponding Gaussian fits. Error bars in (a), (b), and (d) represent one standard deviation. ternary MVL inverter, the intersection region is associated with the transition between the intermediate and logic “0” states, while the intermediate logic state itself arises from voltage division between the two devices. The voltage gain characteristics in Fig. 4d show distinct peaks at each logic transition, confirming sufficient signal discrimination. To estimate the electrical response speed of the inverter, a characteristic switching time (t) was estimated from the charge-balance relationship using Equation (3) \[23\], \[24\], t ≈ C∆VOUT ID,avg , (3) where C is the capacitance estimated from C = CiWL, ∆VOUT is the output-voltage swing, and IDS ,avg is the average drain current within the switching region (VIN = 0.3-0.825 V). Using the measured device parameters, the estimated switch- ing time is approximately 3.35 ms, indicating an electrical response on the millisecond timescale under the constant- current approximation. This value represents a model-based estimate of the characteristic switching timescale rather than an experimentally measured rise/fall time or propagation delay. To evaluate the statistical uniformity of the proposed device structure and fabrication process, we performed a statistical analysis on multiple devices. Fig. 5 summarizes the statistical distributions of the parameters extracted from twenty Ep-AAT devices and twenty ternary inverters. From the transfer curves of the Ep-AAT devices, the VT together with the voltages (Vpeak, Vvalley) and currents (Ipeak, Ivalley) at the peak and valley points were extracted. The VT was found to be −1.19 ± 0.09 V on average, while Vpeak and Vvalley were maintained within narrow distributions of −1.47 ± 0.17 V and −2.04 ± 0.21 V, respectively (Fig. 5a). Regarding the currents, Ipeak and Ivalley were extracted to be 6.7 ± 2.0 × 10−8 A and 3.2 ± 2.2 × 10−8 A, respectively. In addition, the maximum current at VGS = −3 V (Imax) was 1.3 ± 0.9 × 10−7 A, verifying that the current re-increase driven by the P2 channel conduction after the valley appears consistently in all devices (Fig. 5b). Furthermore, to quantify the reproducibility of the inter- mediate logic state, we statistically analyzed the output characteristics of the ternary inverters. Fig. 5c presents the overlaid VTCs of the twenty inverters, in which three distinct logic states are commonly observed in all measured curves. Based on these curves, the deviation ranges of the inverter gain and the intermediate state level were extracted. Each VTC exhibits two transitions, and the gains of the first and second transitions were extracted to be 16.9 ± 2.5 V/V and 7.6 ± 0.9 V/V, respectively, across the twenty curves (Fig. 5d). The intermediate state level, defined as the output voltage at the flattest point of the intermediate plateau where \|dVOUT/dVIN\| is minimized between the two gain peaks, was 0.592 ± 0.047 V, corresponding to a relative variation of about 8%. This confirms that a distinct intermediate state is reproducibly formed in every device. Moreover, the histograms of the two transition voltages (Fig. 5e) show that the two distributions are clearly separated without overlap, confirming that the three logic states are distinguished not only within a single inverter but also across the entire set of devices. These results demonstrate consistent ternary MVL inverter operation across twenty devices without additional circuit complexity. IV. CONCLUSION In summary, we demonstrated an ultralow-voltage ternary inverter based on an Ep-AAT with an engineered dielectric stack. The Ep-AAT exhibits an intrinsic N-shaped transfer characteristic with a clear NTC region, arising from its fully extended p-channel architecture and the combined contribu- tions of the N1, P1, and P2 channels. This characteristic enables three logic states, “1”, “1/2”, and “0”, without additional circuit complexity, with distinct voltage-gain peaks at each transition. Transfer-characteristic analysis further clarifies the ternary-state formation mechanism. Future work will address time-resolved transient characterization to clarify the dynamic circuit performance, including rise/fall behav- ior, propagation characteristics, and frequency-dependent operation, as well as additional processes such as top encap- sulation to further enhance the operational stability. These results suggest that PS/HfO2-based organic Ep-AATs are promising compact and energy-efficient building blocks for next-generation low-voltage MVL circuits. VOLUME 14, 2026 879SEO et al.: DIELECTRIC-STACK-ENGINEERED AATs FOR LOW-VOLTAGE TERNARY LOGIC ACKNOWLEDGMENT (Juhyung Seo and Jihyun Shin contributed equally to this work.) REFERENCES \[1\] S.-W. Jo, J. Choi, R. Hayakawa, Y. Wakayama, S. Jung, and C.-H. Kim, “Organic-semiconductor nanoarchitectonics for multi-valued logic circuits with ideal transfer characteristics,” J. Mater. Chem. C, vol. 9, no. 43, pp. 15415–15421, 2021, doi: 10.1039/d1tc04366h. \[2\] K. Kobashi, R. Hayakawa, T. Chikyow, and Y. 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