# Fileset [manuscript.pdf](https://mdr.nims.go.jp/filesets/52f97cb4-a92d-4a87-8a34-4fa34e930e8b/download) ## Creator [Jiangwei Liu](https://orcid.org/0000-0003-2580-7401) ## Rights [In Copyright](http://rightsstatements.org/vocab/InC/1.0/) ## Other metadata [Hydrogen-terminated and oxygen-terminated diamond metal-oxide-semiconductor field-effect transistors](https://mdr.nims.go.jp/datasets/5b28de28-4596-49be-8b93-6373cabd34ce) ## Fulltext 1 A review paper celebrating the distingushed career of Prof. Yasuo Koide 1 2 Hydrogen-terminated and oxygen-terminated diamond metal-oxide-semiconductor 3 field-effect transistors 4 5 Jiangwei Liu,1, a) 6 1Research Center for Electronic and Optical Materials, National Institute for Materials 7 Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan 8 9 a) Author to whom correspondence should be addressed; electronic mail: 10 liu.jiangwei@nims.go.jp 11 12 Keywords: Single-crystal diamond; H-diamond; boron-doped; MOSFET; logic circuit. 13 14 15 16 17 18 19 20 21 22 23 24 https://samurai.nims.go.jp/profiles?unit=wb0002 Abstract 1 Extensive research has been conducted on wide-bandgap semiconductor diamond for 2 the advancement of high-power, high-frequency, and high-temperature electronic 3 devices. The author has established long-term collaboration with Prof. Koide, focusing 4 on producing p-type hydrogen-terminated diamond (H-diamond) and boron-doped 5 oxygen-terminated diamond (O-diamond) based metal-oxide-semiconductor field-effect 6 transistors (MOSFETs). This paper presents our primary research findings on the 7 fabrication of enhancement-mode H-diamond MOSFETs and MOSFET logic circuits, 8 as well as the high-temperature operation of the boron-doped O-diamond MOSFETs. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 3 1. Introduction 1 To further develop high-power, high-frequency, and high-temperature 2 complementary metal-oxide-semiconductor (CMOS) devices, it is necessary to develop 3 a semiconductor with a large band gap energy, high breakdown field, high carrier 4 mobility, high saturation velocity, and high thermal conductivity. Diamond emerges as a 5 promising candidate for fabricating high-performance CMOS devices [1, 2]. 6 Recently, significant advancements have been made in p-type hydrogen-terminated 7 diamond (H-diamond) and boron-doped oxygen-terminated diamond (O-diamond) 8 channel layer-based MOS field-effect transistors (MOSFETs) [3-12]. Fig. 1(a) depicts a 9 schematic diagram illustrating the accumulation of holes in the H-diamond channel 10 layer. Two-dimensional hole gases (2DHGs) present on the surface of the H-diamond 11 channel layer with a sheet hole density of 1012~1014 cm-2 [14]. The accumulation of 12 2DHGs relies on the existence of surface carbon-hydrogen bonds and negatively 13 charged acceptors. The H-diamond-based MOSFETs have demonstrated remarkable 14 electrical characteristics, including a maximum drain current (ID,max) of 1.35 A/mm [3], 15 a maximum extrinsic transconductance (gm,max) of 206 mS/mm [3], a cut-off frequency 16 of 70 GHz [7], and a robust breakdown voltage of 4266 V [13]. 17 For the p-type boron-doped O-diamond channel layer, the activation energy of 18 boron-doping (0.37 eV) notably surpasses the thermal energy (0.026 eV) at room 19 temperature (RT) [Fig. 1(b)]. Consequently, the hole density is relatively low, resulting 20 in the MOSFETs on the boron-doped O-diamond demonstrating low current outputs [9, 21 10]. Nevertheless, due to no surface thermal sensitivity issue, it is expected that the 22 O-diamond MOSFETs can operate effectively even under high-temperature conditions. 23 Previously, the authors have engaged in long-term collaborations with Prof. Koide, 24 4 focusing on fabricating p-type H-diamond and boron-doped O-diamond based 1 MOSFETs. This paper will provide our primary research findings concerning the 2 fabrication of enhancement-mode (E-mode) H-diamond MOSFETs and MOSFET logic 3 circuits, as well as the high-temperature operation of the boron-doped O-diamond 4 MOSFETs. 5 2. H-diamond MOSFETs 6 2.1 E-mode H-diamond MOSFETs 7 The conditions governing the operation of depletion-mode (D-mode) and E-mode 8 H-diamond MOSFETs have been clarified [15]. Two essential conditions have been 9 identified for the fabrication of E-mode H-diamond MOSFETs: the utilization of a 10 bilayer gate oxide prepared through atomic layer deposition (ALD) and sputtering 11 deposition (SD) techniques, coupled with annealing in the temperature range of 12 150-350 °C [16-18]. Meanwhile, the ALD-oxide/ALD-oxide bilayer and single 13 evaporated oxide insulator on the H-diamond can also lead to the E-mode characteristics 14 for the MOSFETs [19, 20]. On the other hand, despite the existence of an annealing step 15 in the fabrication process of H-diamond MOSFETs with a single ALD-Al2O3 layer as a 16 gate oxide, these MOSFETs continue to exhibit D-mode characteristics [5]. 17 The transition to E-mode behavior in the H-diamond MOSFETs induced by 18 annealing and SD-oxide/ALD-oxide bilayer conditions is attributed to a modification in 19 the transfer doping of the channel layer [15]. Initially, the presence of negative charges 20 at the ALD-oxide/H-diamond interface leads to hole accumulation in the H-diamond 21 channel layer, resulting in the D-mode characteristics in the MOSFETs before annealing. 22 Subsequent annealing leads to the elimination of the negative acceptors or the 23 introduction of compensatory positive charges within the oxide insulator [15]. This 24 5 process significantly reduces the hole density in the H-diamond channel layer, thereby 1 causing the MOSFETs to exhibit E-mode characteristics. 2 Figures 2(a) and 2(c) depict scanning electron microscope (SEM) images of the 3 D-mode ALD-Al2O3/H-diamond and E-mode SD-LaAlO3/ALD-Al2O3/H-diamond 4 MOSFETs, respectively [5]. Schematic cross-sectional structures of these devices are 5 presented in Figs. 2(b) and 2(d), respectively. The distance between the source and drain 6 electrodes for both the Al2O3/H-diamond and LaAlO3/Al2O3/H-diamond MOSFETs is 7 kept at 5.5 µm. However, their gate length (LG) values differ, with the former at 3.0 µm 8 and the latter at 2.0 µm. The interspace lengths between source and gate electrodes 9 (LS-G) and between drain and gate electrodes (LD-G) for the Al2O3/H-diamond MOSFET 10 are 1.2 and 1.3 µm, respectively, while those for the LaAlO3/Al2O3/H-diamond 11 MOSFET are 1.5 and 2.0 µm, respectively. Despite both MOSFETs being designed with 12 the same device structures, variations in the LG, LS-G, and LD-G are observed. These 13 differences are potentially attributed to the positioning accuracy of the laser lithography 14 system, estimated to be around ±1.0 µm. 15 Figures 3(a) and 3(b) display the drain-source current (ID) versus drain-source 16 voltage (VD) characteristics for the Al2O3/H-diamond and LaAlO3/Al2O3/H-diamond 17 MOSFETs, respectively. The gate-to-source voltage (VGS) for both MOSFETs was 18 varied from -10.0 to 6.0 V in increments of +1.0 V, revealing distinct pinch-off and 19 p-channel characteristics in each case. The ID,max values for the Al2O3/H-diamond and 20 LaAlO3/Al2O3/H-diamond MOSFETs are recorded as -112.4 and -69.3 mA/mm, 21 respectively. Normalized on-resistance (RON) values by the gate width (WG) at VGS= 22 -10.0 V are calculated as 56.0 and 63.5 Ω mm for the two devices, respectively. 23 Threshold voltage (VTH) values [Fig. 3(c)] are determined to be 5.3 ±0.1 and -5.0 ±0.1 V 24 6 for the Al2O3/H-diamond and LaAlO3/Al2O3/H-diamond MOSFETs, respectively. 1 Consequently, the Al2O3/H-diamond and LaAlO3/Al2O3/H-diamond MOSFETs operate 2 with D-mode and E-mode characteristics, respectively. Despite the smaller ID,max of the 3 E-mode MOSFET compared to the D-mode MOSFET, their gm,max values are nearly 4 identical at 17 mS/mm [Fig. 3(d)]. This suggests that the current D/E-mode control 5 technique does not compromise the performance of the H-diamond MOSFETs. 6 2.2 E-mode H-diamond MOSFET NOT logic circuits [5] 7 Figures 4(a) and 4(b) depict the top view and schematic diagram of the H-diamond 8 MOSFET NOT logic circuit, respectively. In this setup, Vin, Vout, and VDD represent the 9 input voltage, output voltage, and supply voltage, respectively. The NOT logic circuit 10 comprises a D-mode ALD-Al2O3/H-diamond MOSFET serving as the load device and 11 an E-mode SD-LaAlO3/ALD-Al2O3/H-diamond MOSFET as the driver device. Fig. 4(c) 12 illustrates the voltage transfer characteristics (VTCs) of the H-diamond NOT logic 13 circuit as VDD varies from -5.0 V to -25.0 V, revealing distinctive inversion properties 14 inherent to the NOT logic circuit. In operation, when Vin is at 0 V, the E-mode 15 LaAlO3/Al2O3/H-diamond MOSFET remains in the off-state, leading to Vout closely 16 tracking VDD. Conversely, with Vin set at -10.0 V, the E-mode MOSFET switches on, 17 resulting in Vout near ground level. Consequently, when Vin carries a low logical 0 signal, 18 Vout responds with a high logical 1 signal. The gain curve, defined by -dVout/dVin, is 19 presented in Figure 4(d). The maximum gain value increases from 1.2 to 26.1 as VDD 20 transitions from -5.0 to -25.0 V, showcasing the amplification capabilities of the circuit 21 under varying supply voltage conditions. 22 2.3 E-mode H-diamond MOSFET NOR logic circuits [21] 23 Figures 5(a) and 5(b) display the top view and schematic diagram of the 24 7 H-diamond MOSFET NOR logic circuit, respectively. This NOR logic circuit 1 configuration consists of two E-mode SD-LaAlO3/ALD-Al2O3/H-diamond MOSFETs 2 and a load resistor (RL). Vin1 and Vin2 are representative of the two input voltages, while 3 Vout and VDD denote the output voltage and supply voltage, respectively. The WG and LG 4 for the E-mode MOSFET are maintained at 100.0 and 2.0 µm, respectively. The 5 interspaces between different electrodes for Vin-to-ground, Vin-to-Vout, and Vin-to-VDD are 6 specified as 1.5, 2.0, and 26.0 µm, respectively. 7 Figure 5(c) illustrates Vout as functions of Vin1 and Vin2 for the as-fabricated E-mode 8 H-diamond MOSFET NOR logic circuit. The logic circuit exhibits four distinct states 9 corresponding to logical (1, 1), logical (1, 0), logical (0, 1), and logical (0, 0) input 10 voltage combinations. Each input voltage state is measured over a duration of 60 11 seconds. When both Vin1 and Vin2 are set to -10.0 V, representing the logical (1, 1) state, 12 both E-mode MOSFETs are activated. This results in a substantial current flow through 13 the load resistor, causing a significant drop in VDD. Consequently, Vout converges near 0 14 V, indicating a logical 0 state. When one Vin is set to -10.0 V and the other to 0 V, 15 corresponding to logical (1, 0) or (0, 1) states, only one E-mode MOSFET enters the 16 on-state. Vout again approaches 0 V, reflecting a logical 0 state. When both Vin1 and Vin2 17 are set to 0 V, representing the logical (0, 0) state, both E-mode MOSFETs remain 18 off-state, resulting in no current flow through the load resistor. Consequently, Vout aligns 19 closely with VDD at -10.0 V, indicating a logical 1 state. In summary, when one or both 20 input voltages are “high” signals, the output voltages respond with “low” signals, while 21 both input voltages being “low” signals prompt Vout to exhibit a “high” signal. These 22 observations confirm that the logic circuits are operating with NOR characteristics. 23 Figures 6(a) and 6(b) present the electrical properties of the H-diamond NOR logic 24 8 circuit following annealing at 300 °C and 400 °C, respectively. Following the 300 °C 1 annealing process, the logic circuit continues to exhibit good operation and maintains its 2 NOR characteristics. However, after annealing at 400 °C, the logical characteristics are 3 damaged. When both input voltages are set to 0 V, resulting in the logical (1, 1) state, 4 both E-mode MOSFETs remain in the off-state, causing Vout to approach the VDD of 5 -10.0 V. Conversely, when one or both input voltages are at -10.0 V, representing the 6 logical (1, 0) or (0, 1) states, at least one E-mode MOSFET enters the on-state. This 7 leads to Vout ranging between -4.1 to -7.7 V. Therefore, after annealing at 400°C, there is 8 an increase in the absolute Vout. This is possibly attributed to the degradation of the 9 H-diamond MOSFETs at high annealing temperature [22]. 10 3. Boron-doped O-diamond MOSFETs 11 Due to the exceptional thermal stability of the boron-doped O-diamond electronic 12 devices, our attention was directed towards producing high-performance O-diamond 13 MOSFETs. We focused on investigating their performance through ex-situ and in-situ 14 annealing processes. 15 3.1 O-diamond MOSFETs after ex-situ annealing [23] 16 Figures 7(a) and 7(b) display an SEM image and a schematic diagram of the 17 boron-doped O-diamond MOSFET, respectively. The inset figure in Fig. 7(a) offers a 18 magnified view of the blue square area. The LG, LS-G, and LD-G are measured at 7.0, 9.9, 19 and 17.4 μm, respectively. Additionally, the diameter of the circular-shaped drain 20 electrode is determined to be 597.8 μm. 21 Figures 7(c) and 7(d) depict the ID–VD characteristics for the as-fabricated and ex-situ 22 500 °C-annealed boron-doped O-diamond MOSFETs, respectively. The annealing time 23 was 30 min. The VGS values for both devices range from -16.0 V to 33.0 V in 24 9 increments of +1.0 V. Both MOSFETs exhibit p-type channel characteristics and 1 showcase clear saturation and pinch-off properties. The ID,max values are recorded as 2 -0.49 and -0.6 mA/mm for the B-diamond MOSFETs before and after ex-situ annealing, 3 respectively. Their RON values are measured at 26.9 and 12.8 kΩ mm, respectively, 4 which are much higher than those of the H-diamond MOSFETs [5]. The VTH and gm for 5 the O-diamond MOSFETs are illustrated in Figs. 8(a) and 8(b) respectively. The VTH 6 values for the as-fabricated and ex-situ 500 °C-annealed O-diamond MOSFETs are 7 determined to be 63.2 V and 56.1 V, respectively. For both the as-fabricated and ex-situ 8 500 °C-annealed B-diamond MOSFETs, the gm,max values are determined to be 18.7 and 9 21.4 μS/mm, respectively. 10 3.2 O-diamond MOSFETs at in-situ annealing [24] 11 Figures 9(a) and 9(b) display a SEM image and a schematic diagram of the 12 O-diamond MOSFET, respectively. The drain electrode has a diameter of 299.6 μm, 13 allowing the calculation of the WG as 940.7 μm. The LG is specified as 2.6 μm, with 14 interspatial lengths for the LS-G and LD-G electrodes noted as 5.8 μm and 4.6 μm, 15 respectively. In contrast to the O-diamond MOSFETs in session 3.1, a 20 nm-thick layer 16 of Al2O3 film was applied to cover the sample surface. This Al2O3 cover layer serves to 17 eliminate surrounding environmental effects and edge leakage of electrodes for the 18 O-diamond MOSFETs, thereby enhancing their reliability and device performance. 19 Figures 10(a) and 10(b) illustrate the ID-VD characteristics for the O-diamond 20 MOSFETs operating at RT and 300 °C, respectively. The VGS ranges from -20.0 to 78.0 21 V in increments of +2.0 V. These figures demonstrate efficient operations with p-type 22 characteristics. The ID,max for the O-diamond MOSFET operating at RT is recorded as 23 -1.2 mA/mm. Despite the lower boron doping levels and acceptor concentrations 24 10 (approximately 1016 cm–3 and 6.0 × 1014 cm–3) [24] in this O-diamond channel layer 1 compared to the previous one (approximately 1017 cm–3 and 2.9 × 1016 cm–3) [23], the ID, 2 max exceeds two times the reported value of -0.49 mA/mm. This improvement is likely 3 due to the reduction in LG, LS-G, and LD-G, leading to a decrease in RON from 26.9 kΩ 4 mm to 9.6 kΩ mm. At an operating temperature of 300°C, the ID,max experiences a 5 substantial increase to -10.9 mA/mm, while the RON decreases to 1.1 kΩ mm due to the 6 enhanced activation of boron dopants at higher temperatures. Figures 10(c) and 10(d) 7 depict the ID–VGS characteristics for the O-diamond MOSFETs operating at RT and 8 300°C, respectively. Through linear extrapolation, the VTH values for the MOSFETs at 9 RT and 300°C are determined to be 63.8 ± 0.1 V and 31.2 ± 0.1 V, respectively. The 10 on/off ratios for both MOSFETs exceed 109, marking the highest values reported to 11 date. 12 4. Conclusions 13 This paper provides a summary of key research outcomes concerning the 14 fabrication of E-mode H-diamond MOSFETs and logic circuits, along with insights into 15 the high-temperature performance of boron-doped O-diamond MOSFETs. The 16 operational parameters for D-/E-mode H-diamond MOSFETs have been clarified, 17 leading to the successful fabrication of D-/E-mode H-diamond MOSFET logic circuits. 18 Notably, the E-mode H-diamond MOSFET NOT and NOR logic circuits exhibit robust 19 logical properties. Furthermore, the boron-doped O-diamond MOSFETs demonstrate 20 favorable characteristics following ex-situ annealing at 500 °C and in-situ annealing at 21 300 °C. 22 23 24 11 Acknowledge 1 The author would like to express deep gratitude to Prof. Yasuo Koide for his long-term 2 support and invaluable contributions for my studies in the diamond electronic devices. 3 4 Disclosure Statement 5 No potential conflict of interest was reported by the author. 6 7 Notes on contributor 8 Dr. Jiangwei Liu is currently a Principal Researcher at Semiconductor Defect Design 9 Group of the National Institute for Materials Science (NIMS), Japan. He received his Ph. 10 D. degree from the University of Tokyo in 2012. He worked as a postdoctoral researcher 11 from 2012 to 2013 and as an ICYS Fellow from 2014 to 2016 at NIMS. He became a 12 tenured Independent Scientist from Oct. 2016 and changed to the current position from 13 April 2023. He is presently interested in wide bandgap semiconductors (mainly 14 diamond) based electronic devices and semiconductor physics. 15 16 17 18 19 20 21 22 23 24 https://samurai.nims.go.jp/profiles?unit=5071zz071shttps://samurai.nims.go.jp/profiles?unit=5071zz071s12 References 1 [1] Baliga BJ. Power semiconductor device figure of merit for high-frequency 2 applications. IEEE Electron Dev. Lett. 1989; 10(10): 455-457. 3 [2] Wort CJH, Balmer RS. Diamond as an electronic material. Mater. Today. 2008; 4 11(1-2): 22-28. 5 [3] Hirama, K, Sato H, Harada Y, et al. Diamond field-effect transistors with 1.3 A/mm 6 drain current density by Al2O3 passivation layer. Jpn. J. Appl. Phys. 2012; 51(9R): 7 090112. 8 [4] Kawarada H, Yamada T, Xu D, et al. Diamond MOSFETs using 2D hole gas with 9 1700 V breakdown voltage. Proc. 28th Int. Symp. Power Semiconductor Devices ICs. 10 2016; 483-486. 11 [5] Liu J, Ohsato H, Liao M, et al. Logic circuits with hydrogenated diamond 12 field-effect transistors. IEEE Electron Dev. Lett. 2017; 38(7): 922-925. 13 [6] Ren Z, Zhang J, Zhang J, et al. Diamond field effect transistors with MoO3 gate 14 dielectric. IEEE Electron Dev. Lett. 2017; 34(6): 786-789. 15 [7] Yu X, Zhou J, Qi C, et al. A high frequency hydrogen-terminated diamond MISFET 16 with fT/fmax of 70/80 GHz. IEEE Electron Dev. Lett. 2019; 39(9): 1373-1376. 17 [8] Wang W, Wang Y, Zhang M, et al. An enhancement-mode hydrogen-terminated 18 diamond field-effect transistor with lanthanum hexaboride gate material. IEEE Electron 19 Dev. Lett. 2020; 41(4): 585-588. 20 [9] Pham TT, Pernot J, Perez G, et al. Deep-depletion mode boron-doped 21 monocrystalline diamond metal oxide semiconductor field effect transistor. IEEE 22 Electron Dev. Lett. 2017; 38(11):1571-1574. 23 13 [10] Pham TT, Rouger N, Masante C, et al. Deep depletion concept for diamond 1 MOSFET. Appl. Phys. Lett. 2017; 111(17): 173503. 2 [11] Liu J, Teraji T, Da B, et al. Boron-doped diamond MOSFETs operating at 3 temperatures up to 400 ℃. Funct. Dia. 2025; 5(1): 2450513. 4 [12] Liu J, Teraji T, Da B, et al. Electrical properties of boron-doped diamond 5 MOSFETs with ozone precursor for Al2O3 deposition. IEEE Tran. Electron Dev. 2023; 6 70(5): 2199-2203. 7 [13] Saha N, Eguchi M, Oishi T, et al. High off-state voltage (4266 V) diamond metal 8 oxide semiconductor field effect transistors. J. Vac. Sci. Technol. B 2025; 43: 042201. 9 [14] Sato H, Kasu M. Maximum hole concentration for hydrogen-terminated diamond 10 surfaces with various surface orientations obtained by exposure to highly concentrated 11 NO2, Diam. Relat. Mater. 2013; 31: 47-49. 12 [15] Liu J, Liao M, Imura M, et al. Interfacial band configuration and electrical 13 properties of LaAlO3/Al2O3/hydrogenated-diamond metal-oxide-semiconductor field 14 effect transistors. J. Appl. Phys. 2013; 114(8): 084108. 15 [16] Liu J, Liao M, Imura M, et al. Normally-off HfO2-gated diamond field effect 16 transistors. Appl. Phys. Lett. 2013; 103(9): 092905. 17 [17] Liu J, Liao M, Imura M, et al. Diamond logic inverter with enhancement-mode 18 metal-insulator-semiconductor field effect transistor. Appl. Phys. Lett. 2014; 105(8): 19 082110. 20 [18] Liu J, Liao M, Imura M, et al. Low on-resistance diamond field effect transistor 21 with high-k ZrO2 as dielectric. Scientific Reports 2014; 4(1): 6395. 22 [19] Liu J, Liao M, Imura M, et al. Deposition of TiO2/Al2O3 bilayer on hydrogenated 23 diamond for electronic devices: capacitors, field-effect transistors, and logic inverters. J. 24 https://samurai.nims.go.jp/articles/62ad0d0c-fc9e-4d49-a390-492757db9971https://samurai.nims.go.jp/articles/62ad0d0c-fc9e-4d49-a390-492757db9971https://samurai.nims.go.jp/profiles/liu_jiangweihttps://samurai.nims.go.jp/profiles/liu_jiangweihttps://samurai.nims.go.jp/profiles/liu_jiangweihttps://samurai.nims.go.jp/profiles/liu_jiangweihttps://samurai.nims.go.jp/profiles/liu_jiangwei14 Appl. Phys. 2017; 121(22): 224502. 1 [20] Liu J, Oosato H, Liao M, et al. Enhancement-mode hydrogenated diamond 2 metal-oxide-semiconductor field-effect transistors with Y2O3 oxide insulator grown by 3 electron beam evaporator. Appl. Phys. Lett. 2017; 110(20): 203502. 4 [21] Liu J, Oosato H, Liao M, et al. Annealing effects on hydrogenated diamond NOR 5 logic circuits. Appl. Phys. Lett. 2018; 112(15): 153501. 6 [22] Liu J, Oosato H, Da B, et al. Operations of hydrogenated diamond 7 metal-oxide-semiconductor field-effect transistors after annealing at 500 °C. J. Phys. D: 8 Appl. Phys. 2019, 52(31): 315104. 9 [23] Liu J, Teraji T, Da B, et al. Boron-doped diamond MOSFETs with high output 10 current and extrinsic transconductance. IEEE Tran. Electron Dev. 2021; 68(8): 11 3963-3967. 12 [24] Liu J, Teraji T, Da B, et al. Electrical property improvement for boron-doped 13 diamond metal–oxide–semiconductor field-effect transistors. Appl. Phys. Lett. 14 2024; 124(7): 072103. 15 16 17 18 19 20 21 22 23 24 https://samurai.nims.go.jp/profiles/liu_jiangweihttps://samurai.nims.go.jp/profiles/liu_jiangweihttps://samurai.nims.go.jp/profiles/liu_jiangweihttps://samurai.nims.go.jp/articles/906cfcbe-c633-471a-8ad6-0cd95aea2cf2https://samurai.nims.go.jp/articles/906cfcbe-c633-471a-8ad6-0cd95aea2cf215 Figure captions 1 2 Figure 1. (a) Schematic diagram for 2DHGs accumulation of the H-diamond channel 3 layer and (b) activation energies for diamond with the boron-doping, 4 phosphorus-doping, and nitrogen-doping. 5 Figure 2. (a) SEM images of the D-mode Al2O3/H-diamond and E-mode 6 LaAlO3/Al2O3/H-diamond MOSFETs, respectively. (b) and (d) Schematic 7 cross-sectional structures of them, respectively. 8 Figure 3. (a) and (b) ID-VD characteristics for the Al2O3/H-diamond and 9 LaAlO3/Al2O3/H-diamond MOSFETs, respectively. (c) and (d) ID-VGS and gm-VGS 10 characteristics for both MOSFETs, respectively. 11 Figure 4. (a) Surface morphology for E-mode H-diamond MOSFET NOT logic circuit, 12 (b) VTCs of the NOT logic circuit with the VDD changing from -5.0 to -25.0 V, and (c) 13 the gain curve (-dVout/Vin) derived from the VTCs. 14 Figure 5. (a) and (b) Top view and schematic diagram of the E-mode H-diamond 15 MOSFET NOR logic circuit, respectively. (c) Vout as functions of four Vin states of 16 logical (1, 1), logical (1, 0), logical (0, 1), and logical (0, 0) for the as-fabricated 17 E-mode H-diamond MOSFET NOR logic circuit. 18 Figure 6. (a) and (b) Vout as functions of input voltages for the E-mode H-diamond 19 MOSFET NOR logic circuit after annealing at 300 and 400 ºC, respectively. 20 Figure 7. (a) SEM image and (b) schematic diagram of the boron-doped O-diamond 21 MOSFET, respectively. (c) and (d) ID–VD characteristics for as-fabricated and ex-situ 22 500 ºC-annealed O-diamond MOSFETs, respectively. 23 24 16 Figure 8. (a) ‒DI and (b) gm as functions of VGS for the B-diamond MOSFETs, 1 respectively. 2 Figure 9. (a) SEM image and (b) schematic diagram of the boron-doped O-diamond 3 MOSFET, respectively. (c) and (d) ID–VD characteristics for the O-diamond MOSFETs 4 working at RT and in-situ 300 ºC annealing, respectively. 5 Figure 10. (a) and (b) ID–VGS characteristics for the O-diamond MOSFETs working at 6 RT and in-situ 300 ºC annealing, respectively. (c) and (d) gm-VGS characteristics for the 7 O-diamond MOSFETs working at RT and in-situ 300 ºC annealing, respectively. 8 9 10 11 12 13 14 15 16 17 18 19 20 17 Valence bandConduction band5.47 eVB-doping 0.37 eVN-doping 1.7 eVP-doping 0.57 eVRT thermal energy 0.026 eV(a) (b) 1 2 3 Liu et al., Figure 1 4 5 6 7 8 9 10 11 12 13 18 GateSource DrainLG=2.0 µmLaAlO3/Al2O3/H-diamond MOSFETSource Drain1.5 μm2.0 μmGateH-diamond epitaxial layerDiamond (100) substrate2.0 μmLaAlO3/Al2O3GateSource DrainLG=3.0 µmSource Drain1.2 μm3.0 μmGateAl2O3H-diamond epitaxial layerDiamond (100) substrate1.3 μmAl2O3/H-diamond MOSFET(a) (b)(c) (d) 1 2 3 Liu et al., Figure 2 4 5 6 7 8 9 10 11 12 19 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14048121620 0 -2 -4 -6 -8 -100-20-40-60-80-100-120 0 -2 -4 -6 -8 -100-20-40-60-80-100-120 I D(mA/mm)VD (V)(a) (b)VD (V)8 6 4 2 0 -2 -4 -6 -8 -10 -12 -140-40-80-120-160-200 VTH = -5.0 VVTH = 5.3 V(c) (d)Al2O3/H-diamondLaAlO3/Al2O3/H-diamondAl2O3/H-diamondLaAlO3/Al2O3/H-diamondI D(mA/mm)VGS (V)gm(mS/mm)VGS (V)I D(mA/mm)Al2O3/H-diamond MOSFET LaAlO3/Al2O3/H-diamond MOSFET 1 2 3 Liu et al., Figure 3 4 5 6 7 8 9 10 11 12 20 50 µmVinVoutVDDGroundVDDVinGroundE-mode D-mode(a) (b)0 -2 -4 -6 -8 -10051015202530 0 -2 -4 -6 -8 -100-5-10-15-20-25-30 Vin (V)VDD= -10.0 VVDD= -5.0 VVDD= -15.0 V(c)Vin (V)GainVout(V)(d)VDD= -20.0 VVDD= -25.0 V-5.0 V-10.0 V-15.0 V-20.0 V-25.0 VVDD 1 2 3 Liu et al., Figure 4 4 5 6 7 8 9 10 11 12 13 21 GroundVDDVin1Vin2E-modeE-modeRLVin1Vin2VDDGroundVoutVout(a) (b)50 µm 0-2-4-6-8-10 Vout(V)Vin: 1, 0Vout: 0Vin: 0, 1Vout: 0Vin: 0, 0Vout: 160 s 60 s 60 sTime (s)Vin: 1, 1Vout: 060 s(c) 1 2 3 Liu et al., Figure 5 4 5 6 7 8 9 10 11 12 13 14 22 0-2-4-6-8-10 Vin: 1, 0Vout: 0Vin: 0, 1Vout: 0Vin: 0, 0Vout: 160 s 60 s 60 sTime (s)Vin: 1, 1Vout: 060 s(a)0-2-4-6-8-10 Vin: 1, 0 Vin: 0, 1 Vin: 0, 060 s 60 s 60 sTime (s)Vin: 1, 160 s(b)Vout(V) 1 2 3 Liu et al., Figure 6 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 (a) (b)GateSourceDrainDiamond (100)Source DrainO-diamond7.0 μm9.9 μmGate17.4 μmAl2O3200 μm50 μmGateSourceDrain0 -2 -4 -6 -8 -10 -12 -14 -160.0-0.1-0.2-0.3-0.4-0.5-0.6 VD (V)I D(mA/mm)0 -2 -4 -6 -8 -10 -12 -14 -160.0-0.1-0.2-0.3-0.4-0.5-0.6 VD (V)I D (mA/mm)(d) Ex-situ 500ºC(c) As-fabricatedVG: –16.0 ~ 33.0 VStep: +1.0 VVG: –16.0 ~ 33.0 VStep: +1.0 V 1 2 3 Liu et al., Figure 7 4 5 6 7 8 9 10 11 12 24 60 50 40 30 20 10 0 -10 -200.0-0.1-0.2-0.3-0.4-0.5-0.6-0.7-0.8 30 25 20 15 10 5 0 -5 -10 -150510152025 VGS (V)-(mA/mm)VGS (V)gm(μS/mm)As-fabricatedEx-situ 500 ºCAs-fabricatedEx-situ 500 ºC(a) (b)18.7 μS/mm21.4 μS/mm56.1 V63.2 V 1 2 3 Liu et al., Figure 8 4 5 6 7 8 9 10 11 12 13 25 (a)GateSourceDrain200 μ m Diamond (100)Source2.6 μm5.8 μm 4.6 μmDrainGateO-diamondAl2O3 Al2O3(b)0 -2 -4 -6 -8 -10 -12 -14 -160.0-0.2-0.4-0.6-0.8-1.0-1.2 0 -2 -4 -6 -8 -10 -12 -14 -160-2-4-6-8-10-12 I D (mA/mm)VD (V)VGS: –20.0 ~ 78.0 VStep: +2.0 V(c) RTI D (mA/mm)VD (V)VGS: –20.0 ~ 78.0 VStep: +2.0 V(d) In-situ 300 ℃ 1 2 3 Liu et al., Figure 9 4 5 6 7 26 80 60 40 20 0 -2010-1210-1010-810-610-410-2100102 80 60 40 20 0 -2010-1210-1010-810-610-410-2100102 40 35 30 25 20 15 10 5 0 -5-100102030 40 35 30 25 20 15 10 5 0 -5 -10050100150200250 I D (μA/mm)VGS (V)(a) RT63.8 VOn/off: > 109SS: 315 mV/decVGS (V)I D (μA/mm)(b) In-situ 300 ℃31.2 VOn/off: > 109SS: 570 mV/decVGS (V)gm(μS/mm)215.7 μS/mm29.0 μS/mmVGS (V)gm(μS/mm)(c) RT (d) In-situ 300 ℃ 1 2 3 Liu et al., Figure 10 4 5 6 7 8 9 10 11