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Mu-Pai Lee, Caifang Gao, Meng-Yu Tsai, Che-Yi Lin, Feng-Shou Yang, Hsin-Ya Sung, Chi Zhang, Wenwu Li, Jun Li, Jianhua Zhang, [Kenji Watanabe](https://orcid.org/0000-0003-3701-8119), [Takashi Taniguchi](https://orcid.org/0000-0002-1467-3105), Keiji Ueno, [Kazuhito Tsukagoshi](https://orcid.org/0000-0001-9710-2692), Ching-Hwa Ho, Junhao Chu, Po-Wen Chiu, Mengjiao Li, Wen-Wei Wu, Yen-Fu Lin

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[Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design](https://mdr.nims.go.jp/datasets/d7722aba-0cc0-4ff0-8e3f-663166ecbc3f)

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Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory designAPPL I ED SC I ENCES AND ENG INEER INGSilicon–van der Waals heterointegration for CMOS-compatible logic-in-memory designMu-Pai Lee1, Caifang Gao2, Meng-Yu Tsai3,4, Che-Yi Lin3, Feng-Shou Yang3, Hsin-Ya Sung1,Chi Zhang2,5, Wenwu Li2,5*, Jun Li6, Jianhua Zhang6, Kenji Watanabe7, Takashi Taniguchi8,Keiji Ueno9, Kazuhito Tsukagoshi10, Ching-HwaHo11, Junhao Chu2,5, Po-Wen Chiu4, Mengjiao Li6*,Wen-Wei Wu1*, Yen-Fu Lin3,12*Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic-in-memory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvol-atile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-con-trolled charge trapping/detrapping process and the partially top-gated energy band landscape, the van derWaals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise po-larity tunability, logic nonvolatility, robustness against high temperature (at 85°C), and near-ideal subthresholdswing (80 mV dec−1) can be done. A comprehensive investigation of dynamic charge fluctuations provides aholistic understanding of the origins of nonvolatile reconfigurability (a trap level of 1013 cm−2 eV−1). Further-more, we cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as high-gain (65 at Vdd = 0.5 V) logic gates. This work provides an inno-vative 3D heterointegration prototype for future computing-in-memory hardware.Copyright © 2023 TheAuthors, somerights reserved;exclusive licenseeAmerican Associationfor the Advancementof Science. No claim tooriginal U.S. GovernmentWorks. Distributedunder a CreativeCommons AttributionLicense 4.0 (CC BY).INTRODUCTIONConventional computing schemes based on von Neumann’s archi-tecture are facing challenges due to the growing computationaldemand in modern artificial intelligence technology (1–3). In-memory computing architecture that empowers to overcome thephysical gap between memory and process components is proposedas a promising solution to execute in situ machine learning (4–6).Various electronic devices with nonvolatile memory (NVM) fea-tures, such as resistive memristors, ferroelectric semiconductortransistors, phase change memories, or ionic liquid–gated transis-tors, have been explored to develop robust in-memory computinghardware with analog or digital types (7–12). A key consideration indevice selection is effective area and energy design, coupled withsilicon (Si) back-end-of-line (BEOL) compatibility, consideringthat emerging computing architectures now rely heavily on comple-mentary metal-oxide semiconductor (CMOS) electronics for keyfunctions. For instance, current analog in-memory computingsystems often use Si-based digital computers/converters to com-plete the vector-matrix multiplication accelerator (13–15). On theother hand, digital in-memory computing, such as Boolean logic-in-memory computing, typically requires a high degree of devicereconfigurability to simplify system design—a challenge thatcurrent NVM technologies have yet to adequately address.A specific type of logic transformable device, named reconfigur-able field effect transistor (RFET), distinguishes itself from its coun-terparts and stands out among its counterparts as the dual-gatestructure renders the enhancement of runtime tunability ofcarrier concentration and conductive polarity transformationbetween p- and n-type (16–18). RFETs can be engineered throughthe elaborate design of the Schottky barrier and the selective engi-neering of carrier transport via electrostatic fields. The flexible po-larity reconfigurability can potentially foster compact circuit designwithout compromising accurate logic functions. The original RFETconcept was demonstrated in an axial Si nanowire heterostructurewith independently gated Schottky contact regions (19, 20).However, as the demand for high-density integration continues torise, the ongoing reduction in device size appears to pose a challengeto its electrostatic gating capabilities (21–23). This, in turn, creates achallenge to the device’s reconfiguring efficiency.The utilization of van der Waals (vdW) semiconductors in con-structing RFET exhibits great potential to enhance electrostaticgating efficiency because of their atomic thickness and uniformity(24–26). Recent advances in vdW RFET research have made pro-gress on integrating diverse functions within a single unit, includingtunneling transistors, multiple diode regimes, and ternary logic(27–32). Recent studies have successfully incorporated nonvolatileconductance tunability into vdW RFETs, paving the way for a logic-in-memory prototype for digital computing architectures (33, 34).Nonetheless, these nonvolatile RFETs (NRFETs) rely on a pluri-gatestructure or a metal-ferroelectric-insulator-semiconductor1Department of Materials Science and Engineering, National Yang Ming ChiaoTung University, Hsinchu 30010, Taiwan. 2Shanghai Frontiers Science ResearchBase of Intelligent Optoelectronics and Perception, Institute of Optoelectronics,Fudan University, Shanghai 200433, China. 3Department of Physics, NationalChung Hsing University, Taichung 40227, Taiwan. 4Institute of Electronics Engi-neering, National Tsing Hua University, Hsinchu 30013, Taiwan. 5State Key Labora-tory of Photovoltaic Science and Technology, Department of Materials Science,Fudan University, Shanghai 200433, China. 6School of Microelectronics, ShanghaiUniversity, Jiading, Shanghai 201800, China. 7Research Center for Electronic andOptical Materials, National Institute for Materials Science, 1-1 Namiki, Tsukuba305-0044, Japan. 8Research Center for Materials Nanoarchitectonics, National Insti-tute for Materials Science, 1-1 Namiki, Tsukuba 305-0044, Japan. 9Department ofChemistry, Graduate School of Science and Engineering, Saitama University,Saitama 338-8570, Japan. 10International Center for Materials Nanoarchitectonics,National Institute for Materials Science, Tsukuba 305-0044, Japan. 11Graduate In-stitute of Applied Science and Technology, National Taiwan University of Scienceand Technology, Taipei 106, Taiwan. 12Department of Material Science and Engi-neering, Institutes of Nanoscience, i-Center for Advanced Science and Technology(i-CAST), National Chung Hsing University, Taichung 40227, Taiwan.*Corresponding author. Email: liwenwu@fudan.edu.cn (W.L.); mjli@shu.edu.cn (M.L.); wwwu@nycu.edu.tw (W.-W.W.); yenfulin@nchu.edu.tw (Y.-F.L.)S C I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 1 of 10Downloaded from https://www.science.org on December 08, 2023mailto:liwenwu@fudan.edu.cnmailto:mjli@shu.edu.cnmailto:wwwu@nycu.edu.twmailto:yenfulin@nchu.edu.twhttp://crossmark.crossref.org/dialog/?doi=10.1126%2Fsciadv.adk1597&domain=pdf&date_stamp=2023-12-08structure to control channel conductance and charge storage. Thisscenario poses challenges to retention performance and Si compat-ibility due to the high thermal budget process. This further raiseschallenges in maintaining good device reliability and unlockingthe full potential of vdW RFETs as the device performance is ex-tremely sensitive to its gate-terminal controllability. Consequently,efficient computing approaches call for device configurations andmechanisms to enable efficient collocation of logic and memoryfunctions.In this article, we demonstrate a photo-assisted vdW NRFETdesign for logic-in-memory computing architecture by integratingan ambipolar vdW transistor and a two-dimensional (2D)/3D inter-face. The vdW heterostacking uses the interface between hexagonalboron nitride (h-BN) and SiO2 as a reversible reservoir to constantlyaccommodate photo-induced carriers. Further, the partially top-gated configuration introduces a stair-shaped energy band intothe channel and governs the fast flow of a specific type of carrier.This results in desirable characteristics for logic-in-memory appli-cations, such as photo-induced nonvolatility, robustness againstharsh environments (at 85°C), precisely controllable polarity recon-figurability, and steep slope [subthreshold swing (SS) of 80 mVdec−1]. An in-depth investigation into the dynamic charge fluctuat-ing process near the surface region is further delineated via holisticlow-frequency noise analysis and local Kelvin probe force micro-scope imaging, confirming the universality of the 2D/3D compo-nent with Si BEOL compatibility. In consequence, wedemonstrate a fully complementary inverter with a high gain of65 at a low Vdd = 0.5 V and several logic gate circuits featuringlogic in memory. These achievements mark a notable step towardefficient monolithic integration prototype for shaping the landscapeof RFET-based logic-in-memory technologies.RESULTSDevice of vdW NRFETsThe vdW NRFET is fabricated leveraging the flexible stackabilityand defect engineering capabilities of the vdW family. Figure 1Adepicts the schematic of the vdW stack, which comprises a topgate, an ambipolar transition metal chalcogenide semiconductorchannel, a 2D/3D interface, and a bottom gate. Under the synergeticeffect of the bottom electrostatic field and light illumination, theoriginal transfer characteristics featured with ambipolarity are ex-pected to be tuned between n- and p-type dominant states, as out-lined in the operating sequence shown in Fig. 1B (i). The inherent orinterfacial defects of the 2D/3D blockings serve as a natural reser-voir for storing photo-generated electrons and holes (Fig. 1C). As aresult, the light-induced polarity change can be precisely accuratelyresolved into multiple states and maintained and sustained over along duration without compromising the gate tunability. The topgate regime, demonstrated in Fig. 1B (ii), further molds thedevice’s logic reconfigurability as the engineered energy band land-scapes enable selective carrier injection. With these features, the de-signed vdW NRFET structure consolidates desirable merits for alogic-in-memory computing architecture—including light-induced nonvolatility, precise controllability, and in situ logic re-configurability—all of which will be sequentially introduced.Taking MoTe2-based NRFET as an example, it consists of aMoTe2/h-BN/SiO2 trilayer, a titanium/gold (Ti/Au), and an h-BNlayer functioning as the top gate electrode and dielectric layer, aSi substrate as the back-gate electrode, and two graphene flakes(Gr) as the source/drain electrodes. Scanning transport electron mi-croscopy (STEM) images and elemental mappings of the cross-sec-tional view for both the source/drain electrode region (Fig. 1D) andthe channel region (fig. S1) display the well-distinguished multilay-er, indicating the good crystal uniformity of the fabricated device(fig. S1). The corresponding film thicknesses of Gr, MoTe2,bottom h-BN, and top h-BN are 18, 3, 10, and 17 nm, respectively(see fig. S2). The Raman spectrum collected from the device high-lights typical Raman vibrational peaks: E2g at 1366 cm−1 for h-BN,B12g at 171 cm−1, A1g at ~232 cm−1, E12g at ~288 cm−1 for MoTe2, G at~1581 cm−1, and 2D at ~2917 cm−1 for Gr (fig. S3) (35).Nonvolatile characteristics of the light-induced NRFETThe nonvolatile light-induced polarity change in MoTe2 NRFET isfirst demonstrated under the bottom-gating regime, as the structureschematic shown in Fig. 2A. Initially, it exhibits typical ambipolarconduction behavior with the bottom-gate voltage (Vbg) sweepingfrom −80 to 80 V (Fig. 2B). When the device is exposed to lightillumination alongside the application of a preprocessing electricpulse (pre-Vbg), a notable change in its conduction polarity is ob-served. As highlighted in Fig. 2B, a negative pre-Vbg leads to n-typedominant conduction and a positive one leads to p-type conduc-tion, while no evident changes can be observed under a dark envi-ronment. This suggests that such a polarity change closely relates tothe light signal. Specifically, the p-type and n-type transformationcan be well repeated through a periodic set and reset operations via apair of electric and light pulses, indicating the good reversibility ofthe photo-induced polarity change phenomenon. The time domainof the polarity control among the initial, n-type, and p-type conduc-tion states visually confirms the reversible nonvolatility of the light-induced NRFET (fig. S4). Further quantification of the light tun-ability was undertaken by step-by-step tracking of the changingprocess of the device polarity. Figure 2C shows the incident lightpower density (P)–dependent readout current (Ids) at Vbg = 0V. At P lower than 1 μW cm−2, the photo-generated carrierdensity is limited, leading to a slow change of the readoutcurrent. It then presents a steep linear relationship (P > 1 μWcm−2) between lnIds and lnP with a fitted slope (k) of around 0.8after a pulse pair of light and Vbg. Such a slope can be attributedto frequent charge trapping/detrapping events in this device (36–38). In addition, Fig. 2D plots the Ids as a function of pre-Vbg.When pre-Vbg exceeds 30 V, the readout current at Vbg = 0 linearlyadheres to the variation of 1/Vbg (39–42). This scenario implies thata minimum of 30 V is required to create a narrow barrier for carriersto tunnel through. Consequently, we propose a benchmark forlight-doping studies, considering the light/electrical signal–depen-dent readout current of the NRFET by Ids ∝ Pkexp[(Vbg)−1].An initial investigation into the origins of the photo-induced po-larity change involves analyzing several specific structures. Thetransfer curves recorded for the bottom-gate device—excludingthe bottom h-BN layer—almost remained unchanged followingthe paired stimulation of pre-Vbg and light illumination (fig. S5).This unveils that the main contributions are not from the MoTe2channel or its top or bottom surface, instead confirming the syner-getic role of the h-BN and SiO2 2D/3D interface. Note that the dif-ference between two initial states for device with and withoutbottom h-BN flake originates from the substrate effect, which isan invariance over the whole process. Further insights into theSC I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 2 of 10Downloaded from https://www.science.org on December 08, 2023nonvolatile polarity change in MoTe2 NRFET can be gleaned fromconsidering the charge transport process and energy band evolutiongrounded in interfacial trapping events. As shown in Fig. 2A, thecharge flow driven by paired pulses can be described in threesteps: (i) Under light illuminant, numerous electrons and holesare generated in the ambipolar channel; (ii) at the same time, thepositive (negative) pre-Vbg drives the excited electrons (holes) tomove into the h-BN/SiO2 interface via tunneling-dominant trans-port; (iii) the immersed electrons (holes) are trapped by inherentinterfacial defects, leading to a permanent negative electrostaticfield (positive electrostatic field), i.e., a p-type doping (n-typedoping) effect on the conducting channel. This process rationalizesthe nonvolatility of the light-induced polarity change in bottom-gated MoTe2 NRFET.It is acknowledged that intrinsic defects with donor-like featuresare commonly found in h-BN flakes, and they play a supportive rolein the polarity shift process (43–46). This can be understood by thesketches in Fig. 2A. Electrons in the defects of h-BN can be excitedunder light illumination and contribute to the photocurrent. Theremaining charged ions would reinforce the positive electrostaticfield under a negative pre-Vbg while partially counteracting the neg-ative electrostatic field under a positive pre-Vbg. Consequently, wecan anticipate a stronger n-type doping behavior in h-BN–basedNFET devices compared to the p-type branch. To visuallyconfirm the doping effect of h-BN on MoTe2 NRFET device, a com-parison device that consists of a thicker bottom h-BN layer (>20nm) is investigated (fig. S6). As the thicker h-BN would largelyinhibit contributions from 2D/3D interface, only an n-typedoping behavior is observed. This phenomenon serves a dualpurpose: It indirectly verifies the existence of donor-like defects inh-BN layers and elucidates the dominant role played by 2D/3D in-terfacial defects in achieving the reversible polarity changecharacteristics.The underlying mechanism of the nonvolatilecharacteristicsA clear physical mechanism is crucial for guiding performance op-timization and commercial customization of electronic devices. Togain a visual understanding of how interfacial defects govern thenonvolatile polarity change in the NRFET, dynamic measurementswere carried out using both holistic and local views via charge fluc-tuating noise and Kelvin Probe Force Microscopy (KPFM) technol-ogies. Figure 3 (A and B) and fig. S7 show the mapping plot of theholistic current noise power spectral density (SI) of the device as afunction of frequency and Vbg under different states. At a fixedvoltage, the extracted SI curve versus frequency shows an ideal 1/fvariation signal (Fig. 3, A and B, bottom). The initial logSI mappingand its transfer characteristic, as shown in fig. S7, exhibit a typicalambipolar behavior of the device. It changes to an electron (hole)–dominant conducting feature after the paired light and negative(positive) pre-Vbg stimuli, corresponding to the light-induced n-type (p-type) doped state. The evolution of SI profiles in Fig. 3 (Aand B) mirrors the light-doped transfer characteristics and confirmsthe nonvolatile polarity change in MoTe2 NRFET. The frequencydependency can be defined according to the empirical formulaSI ∝ Iαdsf β , where α and β are the scaling exponents with the current andfrequency, respectively (47, 48). As provided in fig. S8, the fitted βfor all three states near 1 indicates the existence of a uniform distri-bution of charge traps in space and energy, which can be attributedto the fact that the design of 2D/3D heterointegrated structureFig. 1. Nonvolatile vdW RFET. (A) Schematic illustration of nonvolatile vdW RFET, which consists of an ambipolar channel, a 2D/3D heterointegrated interface, and apartially covered top gate configuration. (B) Operating regime of a vdW NRFET with both nonvolatility and reconfigurability. GL1, GL2, and PL represent the top gate line,back gate line, and photo line. (C) Schematic of photo-induced polarity change (n-type doped/p-type doped) and nonvolatile mechanisms. (D) A cross-sectional STEM–High-Angle Annular Dark-Field (HAADF) image of an h-BN/Gr/MoTe2/h-BN/SiO2 heterostructure (source/drain electrode region) stacked on a Si substrate. The corre-sponding energy-dispersive x-ray spectroscopy elemental mappings consider the existing elements of B, N, C, Mo, and Te.S C I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 3 of 10Downloaded from https://www.science.org on December 08, 2023provides a flat interface for charge trapping/detrapping events. Theextracted α values of 2 and Vds-independent SI/Ids2 manifest that thenonvolatile polarity change in the MoTe2 NRFET is rooted in thechannel-surrounded trapping/detrapping phenomena instead ofsource/drain electrodes (fig. S9).The physical images of the 1/f characteristics in MoTe2 NRFETare distinguished to profoundly discuss the charge fluctuating dy-namics under different conditions. First, we found that the normal-ized SI=I2ds as a function of (gm/Ids)2 follows the carrier numberfluctuation model (49, 50). This points out the governing role ofthe interfacial defects during the carrier transport process in aglobal view (fig. S10). The corresponding Nit that represents thetotal density of effective traps is further evaluated (SupplementaryNote). As plotted in Fig. 3C, Nit shows a negligible fluctuation alongwith z/λ for three different conditions because of the uniform dis-tribution of charge trapping/detrapping events in MoTe2 NRFET.The average values of Nit for n-doped and p-doped NRFET are9.35 × 1013 and 3.82 × 1013 cm−2 eV−1, approximately two ordersof magnitude larger than the initial state (5.16 × 1011 cm−2 eV−1).The difference can be understood that the paired light and electricstimuli enhance the charge trapping/releasing process between the2D/3D interface and MoTe2 channel (Fig. 1C). This verifies ourforegoing conjecture about the device mechanisms and confirmsthe heterointegrating design. Note that the slight differencebetween the n-doping level and p-doping level originates fromthe symmetric doping level given the intrinsic defects in h-BNlayers, as shown in Fig. 2A.In comparison to the low-frequency noise characterization thatglobally diagnoses the carrier fluctuations, KPFM characterizationallows for the local examination of the nonvolatility of the light-doping phenomenon in MoTe2 NRFET. It is conducted by monitor-ing the in situ surface potential of the semiconductor channel(Fig. 3D). Following a paired pulse of pre-Vbg and light illumina-tion, the recorded surface potential for a p-type (n-type) dopedstate is lower (higher) than its initial state. This slight reduction (in-crease) in surface potential is attributed to the charge trapping (de-trapping) events from the MoTe2 channel (interfacial state) to theinterfacial state (MoTe2 channel), as explained earlier. The retentionperformance of the device is further tested under harsh conditionsto evaluate its robustness. At room temperature, the readout cur-rents recorded under the n-type and p-type doped states at Vbg =0 show a negligible fluctuation over 104 s (Fig. 3A). This impressiveretention performance can be replicated in eight different states at85°C, underscoring its crucial suitability for memory devices oper-ating in the typical environment (inset of Fig. 3A).Logic reconfigurable characteristic of the NRFETIt is recognized that ambipolar conduction is undesirable in logiccircuit applications due to the leakage current and the associatedenergy costs it incurs. In this regard, we exploit the electrostatic cou-pling of the top gate and MoTe2 channel to reshape the energy bandFig. 2. The photo-induced polarity change in MoTe2 NRFETs. (A) Schematic illustrations of the photo-induced doping behaviors and the corresponding energy banddiagrams for the bottom-gated device at (i) n-type doped and (ii) p-type doped states. (B) Transfer characteristics of the bottom-gated device at its initial, n-type doped,and p-type doped states. (C) Readout current as a function of light power density after paired pulse of pre-Vbg and light illumination. A linear region can be observedwhenthe power density is larger than 1 μW cm−2. (D) The readout current depends on the incident stimulus of paired pre-Vbg and light illumination. The fitted curve indicates alinear relationship between ln(Ids) and 1/Vbg.S C I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 4 of 10Downloaded from https://www.science.org on December 08, 2023landscape and refine the device configuration (Fig. 4A). With gatevoltage (Vtg) sweeping from −10 to 10 V, the recorded transfer char-acteristics after a pair of Vbg and light pulse exhibit typical n-type orp-type unipolar manner (Fig. 4C). A good symmetry and a high on-off current ratio above 106 can be observed. The extracted thresholdvoltages as a function of time in Fig. 4F indicate that the conductingpolarity is highly stable after releasing all external bias (Fig. 4D). Thevalidity of the NRFET device concept is further confirmed by exam-ining more than five devices (fig. S11). Such a scenario can also bereproduced in a purely electrical-operated MoTe2 RFET; however,this requires a constant gate bias (fig. S12). These results collectivelydemonstrate that both the nonvolatile and reconfigurable character-istics can be achieved in MoTe2 NRFET through the collaborativeeffect of the 2D/3D interfacial states, nonvolatile light doping, anddual-gate regime, making it more competitive in in situ logic com-puting architecture based on Si BEOL process (7, 51, 52).The SS of a device is an index of its operating speed and appli-cable bandwidth, which are critical factors for logic circuits andcomputing technologies (53). The SS of the dual-gate MoTe2NRFET is evaluated in Fig. 4E. For both the p-type and n-typebranches, the work current rapidly switches when driven by Vtg,leading to a good SS (80 mV dec−1, taking n-type branch as anexample) near the thermionic limit. This indicates that no evidentcharge disturbance takes place near the semiconductor channelafter the fulfillment of the light-induced charge trapping/releasingat the 2D/3D interface. The energy band evolution is resolved tounderstand the unipolar carrier transport in dual-gate MoTe2NRFET (Fig. 4B). Distinct from the single globe bottom-gating con-figuration, a top gate placed in the middle divides the energy band ofthe MoTe2 channel into three zones. This configuration controls theelectrical characteristic through both the Schottky barrier and thethermionic potential barrier (26, 54). Taking panel (i) as anexample, the channel is initially set to the n-type doped stateunder the paired pulse of negative pre-Vbg and light illumination.When applying a positive Vtg, the middle zone of the MoTe2channel bends downward, reshaping the energy band landscapeof the entire channel into an n-n+-n configuration. The existingSchottky barrier and thermionic potential barrier hinder hole trans-port, resulting in high current in the n-type branch. In contrast, ap-plying negative Vtg locally raises the energy band. This hinders theflow of electrons and holes due to the raised thermionic potentialbarrier in the middle zone and the Schottky barrier. This scenarioleads to a completely off state compared to a typical ambipolar tran-sistor. In consequence, a pure n-type conducting characteristic witha steep slope can be expected under the dual-gate configuration.Similarly, for a positive pre-Vbg, holes dominate the MoTe2channel. The positive (negative) Vtg enables a rare (intensive)carrier flow in the downward (upward) energy band, behaving asFig. 3. The origins of the photo-induced nonvolatile characteristic of MoTe2 NRFETs. (A and B) Mappings of current power spectrum density (SI) versus frequencyand Vbg of MoTe2 NRFET at the n-type doped and p-type doped states, respectively. The dashed lines highlight the evolution of SI at a fixed frequency ( f = 20 Hz). Thebottom panel shows typical SI curves at Vbg = 10 V at these two states that follow the ideal 1/f signal (dashed line). (C) Top: Extracted Nit depending on z/λ for the MoTe2NRFET under the three conditions, where z and λ represent the trap depth and the tunneling distance parameter, respectively. Bottom: Comparison plot of SI/Ids2 and Nitat f = 20 Hz at three states. (D) Evolution of the surface potential of MoTe2 NRFET via in situ KPFM characterization. (E) Retention performance of the device measured atroom temperature (RT) and its multilevel readout currents measured at 85°C.S C I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 5 of 10Downloaded from https://www.science.org on December 08, 2023the pure p-type conduction. In this configuration, one can concludethat the 2D/3D heterointegration and the locally engineered topgate landscape endow the ambipolar vdW channel with nonvolatileand reconfigurable characteristics for in situ executing logicfunctions.The tunable light-induced polarity change underpins the con-trollable reconfigurability of the device. As shown in Fig. 4F, inci-dent signals ranging from the amplitude of pre-Vbg, light pulsewidth, or light power density can modulate the readout current.This controllability originates from the fact that the amount ofthe trapped charges dominates the electrostatic light-doping level.These well-distinguished resistance states offer a broad engineeringspace to customize the threshold voltage of the devices for achievingdesirable logic circuits. We would like to underscore that such anNRFET architecture, with nonvolatile and reconfigurable logiccharacteristics, has potential applications in other vdW stackings,such as WSe2-based NRFETs and ReSe2-based NRFET (fig. S13).These devices share common features such as a 2D/3D dielectricinterface and an ambipolar channel, further confirming the robust-ness of the trap-related device mechanism and the universality ofthe device design.Demonstration of in situ logic computingThe nonvolatility and reconfigurability of the conducting polarityendow NRFETs with the capability to implement in situ logic com-puting on a monolithic channel, i.e., monolithic logic circuit. Itcould potentially take over the traditional Si-based CMOS counter-parts for developing logic computing technologies by circumvent-ing certain complicated manufacturing processes, such as thedefinition of active regions. Moreover, the precise control overFig. 4. The reconfigurable characteristics of MoTe2 NRFETs. (A) Schematic of the dual-gated MoTe2 NRFET with a 2D/3D interface and a partially covered top gateconfiguration. (B) Corresponding energy band diagrams for 2D MoTe2 FETs under the modulation of partially covered Vtg at (i) n-type and (ii) p-type doped states. (C)Statistical transfer characteristics of the top-gated MoTe2 RFETs between n-type and p-type doped states. Each I-V curve are collected after preprogramming by Vbg andlight stimulus. Sweeping the top gate terminal. (D) Retention test of the threshold voltage over 5000 s for the unipolar transfer characteristics under different conditions.(E) Extracted SS (taking n-type branch as an example) as a function of readout current depending on different pre-Vbg (top) and light power density (bottom). The dashedlines behave the value of 60mV dec−1. (F) Multiple-level modulation of the reconfigurability of the device enabled by (i) pre-Vbg, varying from−80 to−20 V for n-type and45 to 80 V for p-type measurement; (ii) the pulse width of pre-Vbg (tbg), varying from 2 to 100 m for n-type and 1 to 60 s for p-type measurement; and (iii) incident lightpower density, varying from 0.1 to 18 nW μm−2 for n-type and 0.06 to 0.2 mW μm−2 for p-type measurement.S C I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 6 of 10Downloaded from https://www.science.org on December 08, 2023multiple levels of threshold voltage and conductance state allows thesymmetric design of the p- and n-type transport characteristics,which is critical for fully leashing the performance of logic circuits.Figure 5A displays the built complementary inverter and itsworking states by a couple of MoTe2 NRFETs fabricated on a mono-lithic vdW channel. To achieve better inverter performance, they arecarefully programmed as one p-type and one n-type devices withsymmetric electrical characteristics, especially in terms of switchingbehavior (fig. S14), using two preprogramming signals (Pre-Vin,Aand Pre-Vin,B). After the preprogramming signals, the conductingstates can be well maintained by the circuit, allowing half-storageof the logic results. Thus, we can use the voltage transfercharacteristics (VTCs) to diagnose the previous information, i.e.,the memory states of the circuit (M). Such a scenario demonstratesthe logic-in-memory computing event. For example, a pair ofsignals of pre-Vin,A = logic 1 and pre-Vin,A = logic 0 are needed toenable the inverter function. After the operation, the pair pre-logicinformation is stored, corresponding to M = 1. As results shown inFig. 5B, the VTC at various supply voltages (Vdd) reveal the full-swing output operation. Such a VTC feature, coupled with ultralowSS and good conducting symmetry, leads to a high gain value of 65at a maximal Vdd (0.5 V), which behaves the good amplification ca-pability of the input signal and switching speed (Fig. 5B, ii). Theideal noise margin (NM) behavior of 0.43Vdd for NML and0.43Vdd for NMH discussed by mirroring the VTC reveals the ro-bustness of the inverter against circuit noise (Fig. 5B, iii). Besides,Fig. 5B (iv) calculates the consumed power (Ps) of the nonvolatilelogic device–based inverter circuit using the formula of Ps = Vdd ×Id. A peak value of 770 pW at Vdd = 0.5 V reveals the importance ofnonvolatility for implementing logic computing.Typical logic gate circuits are further implemented by cascadingNRFET arrays into a logic circuit layout. Figure 5C and fig. S15display the circuit design of AND, OR, NAND, NOR, XOR,XNOR, and corresponding input preprogramming signals. Forexample, a typical NAND circuit is built by assembling two p-type NRFETs in parallel with two n-type NRFETs in series. ItsFig. 5. The demonstration of the logic-in-memory circuits based onMoTe2 NRFET arrays. (A) Schematic of the programmable inverter realized by twoMoTe2 NRFETson a monolithic channel. They are preprogrammed at n-type and p-type. (B) (i) The measured VTC of the inverter at different Vdd varying from 0.1 to 0.5 V. (ii) Calculatedgain values as a function of input voltage (Vin) at different Vdd. (iii) Noise margin characteristics of the inverter at Vdd = 0.5 V. (iv) Calculated power consumption of theinverter versus Vin at different Vdd. (C) Schematics of the programmable logic circuits and the corresponding two preprogramming information for NAND, NOR, XOR, andXNOR gates. (D) Simulated waveforms for operating various logic gate circuits.S C I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 7 of 10Downloaded from https://www.science.org on December 08, 2023simulated waveform is always logic 1 except when four input signalsare all in high voltage (Fig. 5D). Such a circuit layout can also beused as a NOR gate by simply reversing the Vdd and Ground(GND) signals and reconfiguring the polarization of fourNRFETs via electric and light pulses. Therefore, NRFET-enabledlogic circuits allow multiple logic functions in one logic circuit,and the in situ storage of the input history substantially enhancesthe flexibility and efficiency of the circuit design in comparison toconventional CMOS technology.The virtue of fast-speed switching in vdW NRFETs further en-courages us to investigate the generalized in-memory process capa-bility of NRFET-based analog circuits. Taking an output polaritycontrollable amplifier as an example, it was constructed by connect-ing a load resistor (Rload = 10 megohms) with a vdW RFET in series(fig. S16A). Input A (Vin,A), which is the combination of light andVbg signal, determines the conduction polarization of NRFET, andinput B is a dynamic sinusoidal signal (Vin,B) to apply to the topgate. For a negatively programmed input A (n-type), Vout,nshowed the same phase as Vin,B (Vdd = 0.1 V), representing excellentcommon-drain output mode (blue line). For a positively pro-grammed input A (p-type), a 180° phase difference can be observedbetween Vout,p and Vin,B, corresponding to the common-sourceoutput mode (fig. S16B). In this scenario, input A can be in situstored in the circuit, suggesting the signal processing capability ofvdW NRFET-based analog circuits, such as phase-shift keying andfrequency-shift keying.DISCUSSIONIn summary, we have developed a logic-in-memory architecture byintegrating nonvolatility and reconfigurability in one vdW stackingunit, which potentially offers a solution for the area- and energy-efficient computing challenges. The light-induced charge fluctuat-ing behaviors between the ambipolar semiconductor channel andthe 2D/3D interface are responsible for the nonvolatile characteris-tic of the NRFET devices, as visualized by the light-assisted dynamiccharge trapping-detrapping process. The top-gated energy bandlandscape of the vdW channel further reshapes the logic reconfigur-ability of the device. Such scenarios concertedly enable excellentdevice performance for digital computing in reliable photo-induced logic nonvolatility and good controllability over dominantcarrier type, threshold voltage, and multiple resistance states. Thesemetrics can be universally observed in typical ambipolar channels,such as MoTe2, WSe2, and ReSe2, and endow the NRFET units withthe capability for logic-in-memory computing on a 2D/3D mono-lithic heterointegrated structure. Consequently, this work showcas-es the remarkable adaptability and integration advantages of vdWheterostructures in shaping computing technologies.MATERIALS AND METHODSDevice fabricationThe vdW NRFETs were prepared by mechanical exfoliation anddry-transfer method. Taking the heterostructure of h-BN/Gr/MoTe2/h-BN as an example, it was stacked layer by layer on a Si sub-strate with a 300-nm-thick SiO2 layer to form the 2D/3D heteroin-tegration. Then, the top gate, source, and drain electrodes (Ti/Au:15/50 nm thick) were defined by electron beam lithography andthermal evaporation.CharacterizationThe morphology and thickness were measured by optical microsco-py (BX53M microscope with DP26 digital camera; Olympus Corp.)and atomic force microscopy (AFM; Solar TII; Tokyo InstrumentsInc.). Raman spectroscopy was performed with an excitation wave-length of 532 nm (Nanofinder 30 with 523-nm excitation laser;Tokyo Instruments Inc.). The device morphology and its micro-structure were further examined using a field-emission transmis-sion electron microscope (JEM-F200; JEOL Corp.), equipped withan energy-dispersive x-ray spectroscopy system.Device propertiesElectrical characterization of the MoTe2 NRFET was performed in aprobe station (TTPX, Lake Shore Cryotronics Inc.) equipped with asemiconductor parameter analyzer (Keysight, B1500A). Optoelec-trical properties of the devices were characterized under an ultra-long-distance laser beam–shaping module (JadeDot-LDPS,Southport Corp.) combined with an oscilloscope (KeysightDSOX2024a) to modulate light illuminant. The wavelength of theselected laser is 445 nm. To prevent unnecessary fluctuationscaused by the environment, all the electrical measurements wereperformed in a vacuum (<10−5 torr). The dynamic charge charac-teristic measurements were performed on the basis of a program-mable point probe noise measurement system (3PNMS, SynergieConcept) with a system noise floor of 10−27 A2 Hz−1. The currentfluctuations of the device were recorded at a certain bottom-gatevoltage and a source-drain voltage under the initial state, n-typedoped state (a paired pulse of light illumination and −Vbg), andp-type doped state (a paired pulse of light illumination and +Vbg),respectively. For in situ KPFM measurements, a Bruker DimensionIcon SPM system was connected with an external precision sourceunit (Keysight B2912A) to provide a bottom-gate bias pulse. The Pt/Ir conductive AFM probe was used to monitor the variation of thesurface potential under the tapping mode.Supplementary MaterialsThis PDF file includes:Figs. S1 to S16Supplementary NoteREFERENCES AND NOTES1. M. Hutson, Has artificial intelligence become alchemy? Science 360, 478 (2018).2. A. Mehonic, A. J. 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This work was also financially supported by the “Advanced SemiconductorTechnology Research Center” from the Featured Areas Research Center Program within theframework of the Higher Education Sprout Project of theMinistry of Education (MOE) in Taiwan.This study was partly supported by the National Science and Technology Council, Taiwan,under grant no. NSTC 111-2634-F-A49-008. K.W. and T.T. acknowledge support from the JSPSKAKENHI (grant nos. 21H05233 and 23H02052) and World Premier International ResearchCenter Initiative (WPI), MEXT, Japan. Author contributions: Y.-F.L., W.-W.W., M.L., and W.L.conceived and designed the experiments. M.-P.L. fabricated the device and conducted the RFETmeasurements. M.-P.L., C.G., and M.L. completed data analysis. The paper was written by M.L.and Y.-F.L. with contributions from all the coauthors. Y.-F.L. and W.-W.W. supervised theresearch. M.-Y.T., C.-Y.L., F.-S.Y., and C.Z. provided some experimental methods. All the authorsdiscussed the results and commented on the manuscript. Competing interests: The authorsdeclare that they have no competing interests. Data and materials availability: All dataneeded to evaluate the conclusions in the paper are present in the paper and/or theSupplementary Materials.Submitted 5 August 2023Accepted 8 November 2023Published 8 December 202310.1126/sciadv.adk1597S C I ENCE ADVANCES | R E S EARCH ART I C L ELee et al., Sci. Adv. 9, eadk1597 (2023) 8 December 2023 10 of 10Downloaded from https://www.science.org on December 08, 2023Use of this article is subject to the Terms of serviceScience Advances (ISSN 2375-2548) is published by the American Association for the Advancement of Science. 1200 New York AvenueNW, Washington, DC 20005. The title Science Advances is a registered trademark of AAAS. Copyright © 2023 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claimto original U.S. Government Works. Distributed under a Creative Commons Attribution License 4.0 (CC BY).Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memorydesignMu-Pai Lee, Caifang Gao, Meng-Yu Tsai, Che-Yi Lin, Feng-Shou Yang, Hsin-Ya Sung, Chi Zhang, Wenwu Li, Jun Li,Jianhua Zhang, Kenji Watanabe, Takashi Taniguchi, Keiji Ueno, Kazuhito Tsukagoshi, Ching-Hwa Ho, Junhao Chu, Po-Wen Chiu, Mengjiao Li, Wen-Wei Wu, and Yen-Fu LinSci. Adv. 9 (49), eadk1597.  DOI: 10.1126/sciadv.adk1597View the article onlinehttps://www.science.org/doi/10.1126/sciadv.adk1597Permissionshttps://www.science.org/help/reprints-and-permissionsDownloaded from https://www.science.org on December 08, 2023https://www.science.org/content/page/terms-service INTRODUCTION RESULTS Device of vdW NRFETs Nonvolatile characteristics of the light-induced NRFET The underlying mechanism of the nonvolatile characteristics Logic reconfigurable characteristic of the NRFET Demonstration of in situ logic computing DISCUSSION MATERIALS AND METHODS Device fabrication Characterization Device properties Supplementary Materials This PDF file includes: REFERENCES AND NOTES Acknowledgments