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Linfeng Sun, Yishu Zhang, Gyeongtak Han, Geunwoo Hwang, Jinbao Jiang, Bomin Joo, [Kenji Watanabe](https://orcid.org/0000-0003-3701-8119), [Takashi Taniguchi](https://orcid.org/0000-0002-1467-3105), Young-Min Kim, Woo Jong Yu, Bai-Sun Kong, Rong Zhao, Heejun Yang

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[Self-selective van der Waals heterostructures for large scale memory array](https://mdr.nims.go.jp/datasets/2a5aa841-32d7-46e0-b3fb-fb98584843a1)

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Self-selective van der Waals heterostructures for large scale memory arrayARTICLESelf-selective van der Waals heterostructures forlarge scale memory arrayLinfeng Sun1,6, Yishu Zhang2,6, Gyeongtak Han 1, Geunwoo Hwang1, Jinbao Jiang1,3, Bomin Joo4,Kenji Watanabe 5, Takashi Taniguchi5, Young-Min Kim1,3, Woo Jong Yu4, Bai-Sun Kong4, Rong Zhao2 &Heejun Yang 1The large-scale crossbar array is a promising architecture for hardware-amenable energyefficient three-dimensional memory and neuromorphic computing systems. While accessinga memory cell with negligible sneak currents remains a fundamental issue in the crossbararray architecture, up-to-date memory cells for large-scale crossbar arrays suffer fromprocess and device integration (one selector one resistor) or destructive read operation(complementary resistive switching). Here, we introduce a self-selective memory cell basedon hexagonal boron nitride and graphene in a vertical heterostructure. Combining non-volatile and volatile memory operations in the two hexagonal boron nitride layers,we demonstrate a self-selectivity of 1010 with an on/off resistance ratio larger than 103. Thegraphene layer efficiently blocks the diffusion of volatile silver filaments to integrate thevolatile and non-volatile kinetics in a novel way. Our self-selective memory minimizes sneakcurrents on large-scale memory operation, thereby achieving a practical readout margin forterabit-scale and energy-efficient memory integration.https://doi.org/10.1038/s41467-019-11187-9 OPEN1 Department of Energy Science, Sungkyunkwan University, Suwon 16419, Korea. 2 Singapore University of Technology & Design, 8 Somapah Road, 487372Singapore, Singapore. 3 IBS Center for Integrated Nanostructure Physics (CINAP), Institute for Basic Science, Sungkyunkwan University, Suwon 16419, Korea.4 Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea. 5 National Institute for Materials Science, 1-1 Namiki,Tsukuba 305-0044, Japan. 6These authors contributed equally: Linfeng Sun, Yishu Zhang. Correspondence and requests for materials should be addressed toR.Z. (email: zhao_rong@sutd.edu.sg) or to H.Y. (email: h.yang@skku.edu)NATURE COMMUNICATIONS |         (2019) 10:3161 | https://doi.org/10.1038/s41467-019-11187-9 | www.nature.com/naturecommunications 11234567890():,;http://orcid.org/0000-0002-9483-1504http://orcid.org/0000-0002-9483-1504http://orcid.org/0000-0002-9483-1504http://orcid.org/0000-0002-9483-1504http://orcid.org/0000-0002-9483-1504http://orcid.org/0000-0003-3701-8119http://orcid.org/0000-0003-3701-8119http://orcid.org/0000-0003-3701-8119http://orcid.org/0000-0003-3701-8119http://orcid.org/0000-0003-3701-8119http://orcid.org/0000-0003-0502-0054http://orcid.org/0000-0003-0502-0054http://orcid.org/0000-0003-0502-0054http://orcid.org/0000-0003-0502-0054http://orcid.org/0000-0003-0502-0054mailto:zhao_rong@sutd.edu.sgmailto:h.yang@skku.eduwww.nature.com/naturecommunicationswww.nature.com/naturecommunicationsThe use of high-density, fast, and energy-efficient non-volatile memory (NVM) instead of the current flashmemory technology has been explored for unprecedentedapplications, such as the internet of things and neuromorphiccomputing1. For this purpose, the concept of the crossbar arraywith a memory cell at each intersection has been considered themost optimal and promising architecture for more than 60 years2.Although various types of resistive memory cells between wordlines and bit lines in the crossbar array architecture have beenproposed3–8, a fundamental issue remains: the increasing role ofinterconnecting wire resistance and sneak currents in the memoryarray operation as we establish higher integration density (capa-city). The most-studied solution to the above issue, one-selectorone-resistor (1S1R) or one-transistor one-resistor (1T1R) array,still involves complex processes (particularly, current–voltagematching and etching fabrication problems) that are not com-patible with three-dimensional (3D) integration9,10. Anotherimportant solution, complementary resistive switching memory,suffers from its destructive reading operation as well as its highoff-current that causes the sneak current issue11,12. Therefore, anovel device architecture with self-selective memory functionalong with ultralow sneak currents, high selectivity and speed,and reliability are required.Two-dimensional (2D) van der Waals heterostructures haveprovided various breakthroughs for material and device issuesbecause of their unique stability and functionalities13–19.Recently, atomically-thin memory devices have been reportedbased on 2D transition metal dichalcogenides (TMDs);20–22however, they do not have high self-selectivity, which preventslarge-scale integration without using additional transistors.The reliability of TMDs-based memory devices remains anissue as well; the device performance differs from lab to lab23.As we pursue robust device operation with 2D materials, wepaid attention to robust physics researches with 2D materials.Among the diverse 2D elements, two major building blocks,highly insulating hexagonal boron nitride (h-BN)24 andmetallic graphene25,26, are chemically and mechanicallystable, allowing easy stacking processes for vertical hetero-structures and large-scale integration. Although the wafer-scale growths of 2D materials are challenging, a recent reporton wafer-scale single crystal h-BN27 gives a promisingopportunity for industrial applications of 2D materials. Therelatively weak layer-to-layer interaction and strong in-planeatomic bonding nature of 2D h-BN and graphene could beused to realize an original self-selecting function that resolvesthe long-standing issues in the crossbar array.We demonstrate a novel memory cell, a self-selective van derWaals heterostructure, constructed by stacking h-BN and gra-phene layers into a vertical structure of h-BN/graphene/h-BNbetween silver (Ag) and gold (Au) electrodes in a crossbar arraystructure. The unique roles of 2D materials (h-BN and graphene)in our self-selective memory can be described like below. First, thestrong in-plane atomic bonding of high-quality h-BN layersprovides a platform for ultralow off-state current and theendurance against high on-state currents (0.3 mA). Second, thestrong in-plan atomic bonding of transferable graphene efficientlyblocks the diffusion of Ag filaments, which can generate a voltageacross the other h-BN layer without any Ag substance. With theassistance of graphene, our van der Waals heterostructure coulddemonstrate the volatile and non-volatile dynamics in one cell.We note that the graphene cannot be replaced by other typicalmetals because Ag filaments can be easily diffused through thosemetals. Accordingly, our self-selective 2D memory cell based onh-BN and graphene resolves the current–voltage matchingand integration issue of 1S1R and destructive read operationissue of complementary resistive switching, demonstrating aself-selectivity of 1010 with an on/off resistance ratio larger than103 and an operation time constant of tens of nanoseconds in theheterostructure.ResultsSelf-selective memory operation. The self-selective van derWaals heterostructure memory cell, h-BN/graphene/h-BN, andits working mechanism with a possible sneak current path in acrossbar architecture are schematically described in Fig. 1a. Thedevice fabrication steps and their optical image and Ramanmapping are shown in the supplementary materials (Supple-mentary Figs. 1 and 2). Under the crossbar array structure withasymmetric Ag (for word lines) and Au (for bit lines) electrodes,the h-BN/graphene/h-BN structure is introduced at each inter-section (Fig. 1a). A single memory cell exhibits characteristicmemristive current–voltage (I–V) curves in positive voltage rangeas shown in Fig. 1b (a whole I–V curve ranging from negative topositive voltages is shown in Supplementary Fig. 7) where thevoltage and current ranges are chosen to describe how the self-selective memory operates. Thus, the voltage and current rangesin Fig. 1b are categorized into four ranges: ranges “1” and “3”indicate the I–V performance of numerous unselected memorycells with inevitably applied voltages under a one-half (V/2) orone-third (V/3) voltage bias scheme, while ranges “2” and “4”indicate the I–V performance of a selected memory cell with ahigh-resistance state (HRS) and low-resistance state (LRS),respectively.In Fig. 1b, a HRS/LRS conductance ratio of 103 and a self-selectivity ratio of 1010 (defined as the resistance ratio of selectedand unselected memory cells with probing voltages) aredemonstrated in a single device operation. They are key featuresof our 2D self-selective cell, which is distinguished from formerself-rectifying cells (see Supplementary Table 1).The wide voltage windows for non-selective cells and theselected cells to enable a selectivity of beyond 1010 give sufficientvoltage margins for various architectures and engineering.Moreover, the selected-state current (LRS and HRS) and thresh-old voltage could be tuned by the thickness of h-BN layers. Thesimilar results on the thickness of switching layer-dependentswitching behaviors have been reported in previously works20,28.We investigated a thinner h-BN based-device (SupplementaryFig. 3) showing a lower set voltage and on-state current; thisenables tunable voltage and current for different applications.Further engineering for practical set voltages via controlling thethickness of h-BN layer is promising.Microscopic origin for the selectivity. High-resolution trans-mission electron microscopy (HR-TEM) was used to prove theunique dynamics for memory operation in the self-selective cell.We analyzed the cross-sectional images of a pristine memory celland a memory cell after successive memory operation, a so-called‘formed device’, by HR-TEM (Supplementary Figs. 4–6). Our in-situ TEM study could not produce reliable data due to the toolarge heat confinement and mechanical stresses applied to ourdevice in the sample holder as similarly reported in the previousstudies29. Instead, our ex-situ TEM study (see SupplementaryFigs. 5 and 6), allows us to investigate more realistic deviceoperation in our self-selective cell.In the cross-sectional image of a ‘formed memory device’, weobserved partial Ag layers between the graphene and bottom h-BN layer (Supplementary Fig. 5), which results from themigration of Ag ions through the h-BN layer during the memoryoperation; however, no Ag filament inside the bottom h-BN layerwas observed in the ‘formed device’ by HR-TEM, indicating thevolatile nature of the Ag filament at zero voltage bias. The volatileARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-11187-92 NATURE COMMUNICATIONS |         (2019) 10:3161 | https://doi.org/10.1038/s41467-019-11187-9 | www.nature.com/naturecommunicationswww.nature.com/naturecommunicationsswitching behavior of the unstable Ag filaments could beexplained by the stable and strong in-plane atomic bonding ofh-BN and the chemically inert interface between the h-BN andgraphene layer. The discontinuous or broken state of the Agfilament at zero bias is kept until a voltage above 2.6 V is newlyapplied; below 2.6 V and without the Ag filaments, the hightunneling resistance of 15 nm thick h-BN generates low currentstates (with a resistance larger than 1014 Ω) in ranges “1” and “3”(Fig. 1b, c).Once conductive Ag filaments are formed in the h-BN layerbetween the Ag electrode and graphene by a newly appliedvoltage larger than 2.6 V, the total memory resistance isdominated by the presence of conducting paths formed by themigration of boron vacancies in the h-BN layer between theAu electrode and graphene; a low activation energy and non-volatile memory behavior of the boron vacancies without Agelectrodes have been reported30,31. A defective path that canact as a boron vacancy filament was observed between the Auelectrode and graphene (see Supplementary Fig. 6). It has beenreported that such conducting paths through boron vacanciesshow non-volatile transport via trap-assisted space chargelimited conduction that can be used as NVM;30,31 thus, ranges“2” and “4” in Fig. 1b, c indicate the non-volatile HRS andLRS. Finally, a voltage larger than 4 V converts the HRS to theLRS by creating non-volatile conducting paths composed ofboron vacancies; these non-volatile conducting paths can bebroken by applying an opposite voltage bias (−4 V) in thereset process (Supplementary Fig. 7a)28. The correspondingelectroforming processes are shown in Supplementary Fig. 8.Memory integration with low sneak current. The memoryperformance of integrated self-selective van der Waals cells in thecrossbar array was evaluated using a one-half (V/2) bias voltagescheme, as shown in Fig. 2. The schematic illustration of a self-selective memory crossbar array with a selected memory cell(highlighted in pink color) in Fig. 2a describes a reading opera-tion with voltage application in a V/2 bias voltage scheme; a netvoltage of “V” is applied to the selected cell. Among the eightunselected cells, four cells (highlighted by a light clear pink color)still experience a voltage of “V/2”, while the other four cells (violetcolor) have zero applied voltage. According to the single cellperformance is shown in Fig. 1, the eight unselected cells haveapplied voltages below the threshold voltage of 2.6 V and thuspossess a resistance larger than 1014Ω. The reliability of theunselected cells, indicated by the cumulative probability of theHRS, is demonstrated in Fig. 2b. The non-volatile LRS and HRSalso exhibit stable operation (steady resistances of LRS and HRSin Fig. 2b). To show the statistic performance, the cumulativeprobability of HRS, LRS based on the device to device variation(144 devices) is shown in Supplementary Figs. 9 and 10.Based on the performance of a single self-selective cell, a SPICEmodel was built to explore the evolution of readout margin andenergy efficiency as we increase the integration capacity with ourself-selective memory cells. The current vs. voltage curve over thefull-operation voltage range (from −5 to+ 5 V) was simulatedfirst to determine the validity of our SPICE simulation (the fittedI–V curve and the reading bias voltage scheme are shown inSupplementary Fig. 7a). Then, the readout margin and energyefficiency of the integrated cells are simulated by SPICE modelinga0 1 2 3 4 5AuBNGBNAg10–1610–1210–810–4VddVoutRsRj1, 324Current (A)Voltage (V)Vread VwriteWorldlinesBitlinesV < Vread cbHRS NVM LRS NVMNon-selectedmemory cell(V < Vread )Selectedmemory cell(V > Vread )1234Fig. 1 Crossbar memory array of a self-selective van der Waals heterostructure and the working mechanism. a Schematic picture of the van der Waalsheterostructure in the crossbar memory array architecture, differing from the traditional one-selector one-resistor and complementary resistive switching(see in the main text). b Current–voltage characteristics of a single memory cell. The four current and voltage ranges represent four different states of thememory cell. The selectivity of the self-selective cell is 1010, with a big memory window (103). Our unit cell shows bipolar behavior. For the negative voltagedirection, it is shown in Supplementary Fig. 7a. During the measurement, the top electrode (gold) was kept to connect the ground. c Schematic illustrationof hexagonal boron nitride/graphene/hexagonal boron nitride layers for the four states in ‘b’. Ranges “1” and “3” represent the high-resistance state andlow-resistance state of unselected cells, respectively. Ranges “2” and “4” represent the high-resistance state and low-resistance state of a selected memorycell, respectively. Conductive silver filaments are formed at a voltage of 2.6 V, enabling the read of the high-resistance state (range “2”) and low-resistancestate (range “4”) in a voltage window from 2.6 to 4.0 V. The gray, purple, blue, and yellow spheres represent silver, hexagonal boron nitride, graphene, andgold layer, respectively. The white spheres in the top hexagonal boron nitride layer represent the boron vacancies in hexagonal boron nitrideNATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-11187-9 ARTICLENATURE COMMUNICATIONS |         (2019) 10:3161 | https://doi.org/10.1038/s41467-019-11187-9 | www.nature.com/naturecommunications 3www.nature.com/naturecommunicationswww.nature.com/naturecommunications(Fig. 2c, d). The readout margin in Fig. 2c demonstrates a valueclose to 100% up to megabit-scale (106) capacity with variableinter-cell wire resistances. We note that practical readout marginis kept until terabit-scale integration in Fig. 2c; the readoutmargin is above 45% at a terabit (1012) capacity even with a wireresistance of 10Ω (10Ω is enough for our case, see Methods),larger than the acceptable value (10%)32,33. Therefore, the LRSand HRS of memory can be easily distinguished with an effectivemargin for terabit-scale integration. The one-third (V/3) voltagescheme exhibits similar results (Methods and SupplementaryFig. 11). Further advanced synthesis technique of graphene andh-BN could realize the large-scale integration.The influence of sneak current can be directly quantified bycomparing the power consumption in the selected and all otherunselected memory cells. Accordingly, the capacity-dependentpower consumption with different wire resistances in integratedmemory cells is simulated by SPICE modeling, as shown inFig. 2d. Even at a one terabit-scale, the power consumption ratioreaches 10% with the wire resistance set as 10Ω; one selected cellconsumes 10% of the total power that the total 1012 cellsconsume. In other words, the sneak current is greatly suppressedwith our self-selective van der Waals structure. We note thatstate-of-the-art power efficiency at an array size of 105 remainsonly 0.02%5. This finding is consistent with the selectivity ofbeyond 1010 described in Fig. 1b, demonstrating that our self-selective memory cells effectively suppressed sneak currents,which cannot be demonstrated by other conventional devices(Supplementary Table 1).The endurance and reliability of volatile and NVM behaviorsin our self-selective memory cells were examined over 106 write-and-reset cycles, and the results are summarized in Fig. 3a. Ourdevice is much more stable than previously reported 2Dmaterials-based memory cells with limited switching cycles ofhundreds of cycles19,20,28,34,35. A voltage pulse of 6 V (−6 V) for atime duration of 0.1 ms was used to set from the HRS to the LRS(reset from the LRS to the HRS) in the cell. A reading voltage of3 V and a smaller voltage (1.5 V under a one-half voltage biasscheme) for the unselected cell state followed each write-and-resetprocess. Steady currents for the LRS (red dots), HRS (blue dots),and one-half reading voltage (violet dots) over 106 cycles wereobserved, as shown in Fig. 3a. In addition, we confirmed that allthree states are stable over 10 6 s (Fig. 3b), originating from thevan der Waals heterostructure with the two most stable 2Delements (h-BN and graphene).Switching speed between memory states is a key factor in ahighly integrated self-selective memory array outperforming thecurrent flash memory technology7. The red curve in Fig. 3cexhibits a typical transient switching behavior with a timeconstant of tens of nanoseconds in our self-selective cell by awriting voltage pulse. After the pulse, the zero voltage biasmakes the memory cell be in a non-selected state within a similartime-scale (<50 ns). Based on the results shown in Fig. 3c, we canalso estimate the energy for ‘write’ operation as 1.5 nJ (the pulsewidth, amplitude, and current are 0.5 μs, 10 V, and 0.3 mA,respectively), which is almost 1000 times smaller thanthose of flash memory36. The current density of our device is103 106 109 1012 101502550751001 k 1 M 1 G 1 T406080Readout margin (%) 1000.1 1 10110100aCapacity (bit)0 Ω1 Ω10 Ω 0 Ω1 Ω10 Ω Wire resistancePower efficiency (%)@ 1Tbit capacityc dResistance (Ω)Wire resistance (Ω)Cumulative probability (%)½ VreadLRS HRS (Vread)bSelectivity>1010Capacity (bit)1 k 1 M 1 G 1 T10100Power efficiency (%)–1/2 V0 V0 V0 V0 V1/2 VFig. 2 Memory integration of self-selective memory cells. a Schematic picture of a reading process using a one-half voltage scheme. The selected memorycell with a net voltage application of ‘V’ is highlighted in pink, while either one-half ‘V’ or zero voltage bias is applied to the other memory cells. b Reliabilityof the three states: the low-resistance state (probed by Vread), high-resistance state (probed by Vread), and unselected state (probed by one-half Vread)exhibit narrow voltage windows and a high selectivity of larger than 1010 in the cumulative probability of resistances. c Readout margin for three differentwire resistances between neighboring cells simulated by using SPICE modeling. A 1/2 V voltage scheme was used in the simulation, while a 1/3 V voltagescheme showed a similar result (Supplementary Fig. 11). d Simulated capacity-dependent energy efficiency with three different wire resistances. An energyefficiency of 10% was observed at an integration capacity of one terabit by SPICE modeling, which is consistent with the greatly suppressed sneak currentdue to the high selectivity of larger than 1010 in (b). The unit wire resistance calculated in our work is less than 10Ω (see Methods). Thus, the maximumwire resistance used for this simulation is 10ΩARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-11187-94 NATURE COMMUNICATIONS |         (2019) 10:3161 | https://doi.org/10.1038/s41467-019-11187-9 | www.nature.com/naturecommunicationswww.nature.com/naturecommunications~3 × 104 A/cm2 (ON-state current divided by device area around1 μm2), which is much lower than that of conventional flashmemory (106 A/cm2)37. We note that the operation voltage andcurrent can be optimized through process and device engineeringto further reduce energy consumption. Another important factorfor practical applications of memory arrays is device stability overa wide range of temperatures: due to the highly stable propertiesand non-sensitive to ambient of h-BN24,38, increased tempera-tures in real applications or extreme temperature environmentsproduce steady currents or memory states in our self-selectivememory cells, as shown in Fig. 3d.Demonstration of self-selective memory array with 2Dmaterials. Programming and reading 144 binary bits in a 12 ×12 crossbar array of our self-selective memory cells withinlateral dimensions of 15 × 15 μm2 are demonstrated as aproof-of-concept in Fig. 4. Given the large selectivity of 1010of the memory cell, all three conventional programmingschemes, namely, floating, one-half voltage, and one-thirdvoltage schemes, can be applied in the memory crossbar arraywith a sufficient readout margin and energy efficiency. InFig. 4, as an example, a 5 V writing voltage was chosen. Thus,only the selected cell is programmed, while the current flowingthrough all other unselected cells is kept at an extremely lowlevel (below 10 fA). We note that the ultralow sneak current(10 fA) is also maintained during the reading operation.Based on the 12 × 12 crossbar arrays of our self-selectivememory cells, a code of “SKKU” was programmed using 144binary bits for four letters (SKKU), as shown in Fig. 4b. Eachintersection of a bit line and a word line has an address numberand a non-volatile conductance as the binary information(Fig. 4b), which can be combined to register the intended code.Moreover, the self-selective memory operation was validated on aflexible substrate, polyethylene terephthalate (PET) (Supplemen-tary Fig. 12). The full operation of a single memory cell on PETover a voltage sweep following sequential numbers and arrows isshown in Fig. 4c. The I–V curve in Fig. 4c is similar to the fulloperation curve (Supplementary Fig. 7a); in the measurements, acompliance current of 10–4 A was applied for reliable operation,and a reading voltage window ranging from 2.3 to 3.7 V and awriting voltage window (>4 V) were observed along the sequentialnumbers and arrows (Fig. 4c).DiscussionOur self-selective memory based on a van der Waals hetero-structure (h-BN/graphene/h-BN) resolves a fundamental issue,sneak currents, over a large voltage window, which overcomesformer memristive devices (e.g., 1S1R, 1T1R, or complementaryresistive switching). This advancement opens a door for large-scale and energy-efficient memory integration with a wafer-scalegrowth of few-layered high quality h-BN. The unique stabilityand impermeability of graphene and h-BN provide break-throughs, such as atomic valves for Ag ions and the boronvacancy kinetics in h-BN, for the novel and stable memoryoperation. Thus, our new memory device allows efficient crossbarmemory arrays on flexible substrates for future memory appli-cations, such as the internet of things and wearable artificialintelligence.MethodsDevice fabrication procedures. The 2D materials (graphene and hBN) aretransferred on a silicon substrate with a 300 nm dry oxide layer (SiO2) on its topsurface. HOPG (highly ordered pyrolytic graphite) crystal was purchased from HQGraphene and h-BN crystal was obtained from Prof Takashi Taniguchi’s group atthe National Institute of Materials Science, Japan. First, the bottom electrode (BE,Ag) with a pre-designed pattern was deposited on the Si/SiO2 substrate. Next, theh-BN flake was exfoliated on the polydimethylsiloxane (PDMS) substrate andtransferred onto the BE by a typical dry-transfer technique. Then, the graphene300 350 400 45010–1810–1310–810–3a b–30369120 1 20.00.10.20.30.4c dCurrent (A)Operation time (S)Voltage (V)Current (mA)Time (μs)Current (A)Temperature (K)LRS @ VrHRS @ VrCurrent (A)Measurement cycles6 V3 V 1.5 VWriting and reading cycle schematic100 101 102 103 104 105 106 102 103 104 105 106Read @ Vr12LRS @ VrHRS @ VrRead @ Vr12LRS @ VrHRS @ VrRead @ Vr1210–1710–1310–910–510–1710–1310–910–510–1103Fig. 3 Stability and switching speed of our self-selective memory. a Endurance of switching behavior among the three states by a voltage pulse train over106 measurement cycles. The resistance states were read by a wide pulse width to avoid the net charge (See Methods). b Retention behavior of thethree states for a time of 106 s. c Switching speed during programming operation shows a time constant of tens of nanoseconds. A voltage pulse of 10 V for500 ns was used for the measurement. d Stability of the three states (low-resistance state, high-resistance state, and unselected state) over temperaturesranging from 290 to 450 K, due to the high crystal quality of hexagonal boron nitride and grapheneNATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-11187-9 ARTICLENATURE COMMUNICATIONS |         (2019) 10:3161 | https://doi.org/10.1038/s41467-019-11187-9 | www.nature.com/naturecommunications 5www.nature.com/naturecommunicationswww.nature.com/naturecommunicationslayer exfoliated on the prepared PDMS substrate was transferred onto the h-BNlayer with a smaller size than that of the h-BN layer below. The same transfertechnique was used again to transfer another h-BN layer on top of the graphenelayer. Then, only the h-BN and graphene layers at the target united cell area werekept, and all other parts were etched by RIE. Finally, gold was deposited by athermal evaporator to form the top electrode (TE) in the pre-designed area. Duringthe dry-transfer technique, the layer-by-layer alignment was assisted by opticalmicroscopy.Device patterning details. The patterning of both TE and BE was designed byelectron beam lithography (EBL). First, the silicon substrate with a 300 nm dryoxide layer was spin-coated with poly (methylmethacrylate) (PMMA) 950 A4. Thespin speed was 500 rpm for the first 5 s and it was increased to 4000 rpm for 60 s.Then, the sample was baked at 120 °C on a hot plate for 2 mins. Next, EBL wasused to expose the pre-designed electrode pattern, and then a typical developingprocess was employed. Finally, silver (Ag) deposition was conducted by a thermalevaporator, followed by a 2 h lift-off process in acetone. Then, the dry-transfertechnique was used to transfer the heterojunctions on the prepared Ag electrode.After that, the same EBL patterning processing as mentioned above was used forpatterning the TE (Au). The metal deposition method for the Au electrode wasthermally evaporated. For the flexible device, photolithography was used to fab-ricate the patterns on a PET substrate with LOR 2 A and AZ GXR-601 as double-layered photoresists (PRs) as follows: (1) LOR 2 A (MicroChem Corp) was spin-coated on the PET substrate (500 rpm for 5 s and then 3000 rpm for 30 s), followedby AZ GXR-601 (AZ electronic materials Co. Ltd) with the same spin speed. Then,the sample was baked on a hot plate at 110 °C for 1 min. (2) The sample wasexposed under UV light for 10 s with a mask aligner machine and photo mask. (3)The sample was dipped into the AZ 300 MIF developer (AZ Electronic MaterialsCo. Ltd) for 20 s to remove the exposed PR. (4) Metal deposition of Ag with athickness of 50 nm was performed, followed by lift-off with AZ 100 remover (AZElectronic Materials Co. Ltd.). (5) The heterostructure (h-BN/graphene/h-BN) wastransferred onto the pre-designed Ag electrode. (6) The same photolithographyprocesses were conducted with the TE materials as Au at 50 nm.Optical characterization. Raman spectra and images were measured with a WitecAlpha300 confocal system located in a glove box to avoid the effect of H2O or O2on the measurements. The concentrations of H2O or O2 were 0.6 ppm and 0 ppm,respectively. The laser wavelength for both the Raman spectra and images was532 nm, and the grating used for the measurement was 600 mm−1. The integrationtime for single spectra and images were 10 s and 0.2 s, respectively. The laser powerwas kept below 0.5 mW to avoid heating effects on the samples. A 100x objectivelens (Zeiss) was used to focus the laser beam.Key electrical measurement conditions. Electrical measurements were per-formed at room temperature in vacuum, using a Keithley 4200 semiconductorparameter analyzer and a Cascade probe station. Two modules were used: a directcurrent (DC) source unit (4200-SMU) with high precision pre-amplifiers and a4225-PMU waveform generator unit for pulse measurement. During DC and pulsetesting, the positive voltage output was connected to the Ag (BE). The Au (TE) waskept as the ground electrode. During the pulse testing, the maximum current rangewas set to 10 mA, which sets the current resolution at 1 µA. Initially, all deviceswere at high resistance in the initial state and were SET to the LRS with a 100 µs/6V pulse and RESET to the HRS with a 100 µs/-6 V pulse. The resistance states wereread with 5 ms/± 3 V pulses that cannot change the device state but just open theoff-state. The RESET and SET voltages are higher than those measured with DCsweeps (VSET= 4 V, VRESET=−3.8 V at DC).SPICE modeling. The resistive switching curve of the self-selective memorydevice based on a van der Waals heterojunction (h-BN/graphene/h-BN) shown inFig. 1b was modeled using Verilog-A. The large-scale crossbar array structurebased on this device was simulated using Cadence Spectre. Detailed descriptions ofdevice modeling and large-scale array simulation are provided (SupplementaryFigs. 7 and 11).As shown in Supplementary Fig. 7, two kinds of bias voltage schemes were usedin this simulation. (a) The one-half voltage bias scheme: The voltage is appliedacross the selected word and bit line, while all other bit and word lines are appliedwith a half voltage bias. As shown in Supplementary Fig. 7b, there will be no biasvoltage applied to the cells in the gray-colored background. In contrast, the cellswithin the magenta-colored area are half-voltage biased. In our self-selective vander Waals heterostructure-based memory cells, the sneak path current can bedramatically suppressed to less than 10−14 A for half-biased cells due to extremenon-linearity and high-selectivity behaviors. (b) The one-third voltage bias scheme:in this case, the selected word line is fully biased, while the selected bit line isgrounded. Then, the unselected word lines and bit lines are biased at 1/3 and 2/3 ofthe full bias voltage, respectively. Therefore, the cells within the gray-colored areaare under one-third of the full bias voltage, and the cells in the magenta-coloredarea are under one-third of the full bias voltage.In this simulation, the wire resistance is selected as 0Ω, 1Ω, or 10Ω,respectively. In our work, the wire resistance is much less than 10Ω. Theevaluation details are as below: supposing that the feature size is F, L= 2 F, andS= F*T, where T denotes the wire thickness (in our work, the thicknesses of boththe Ag and Au layers are 50 nm). The unit wire resistance= ρL/S, and theresistivity of Ag and Au is 15.87 nΩ m, and 22.14 nΩ m, respectively. This gives theresistance of Ag and Au as 0.635Ω and 0.88Ω, respectively, which are much lowerthan 10Ω.Data availabilityAll data needed to evaluate the conclusions in the paper are present in the paper and/orthe Supplementary Materials. Additional data related to this paper are available from theauthors on reasonable request; see author contributions for specific data sets.a cbCurrent (A)Bit linesWord lines12 × 12 crossbar arraysConductance (μS)Bit line (#) Bit line (#) Bit line (#) Bit line (#)Word line (#)–41234561 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 7 8 9 10 11 12123456789101112710210110010–110–289101112–2 0 2 410–1810–1510–1210–910–610–39Voltage (V)1234856710Fig. 4 Programming a code using a crossbar array with our self-selective memory cells. a Optical and scanning electron microscopy images of a 12 × 12crossbar memory array with our self-selective van der Waals heterostructure experimentally. Scale bars: 200 and 5 μm for the optical and SEM images,respectively. b The color map of the readout conductance with a reading voltage of 3 V (one-half voltage scheme). The heavy violet color indicates a lowerreadout conductance, as shown in the conductance scale. c A full-voltage-range resistive switching curve of a self-selective cell fabricated on flexible PETsubstrate. The sequential numbers and arrows exhibit typical write and erase processes, maintaining the negligible sneak current for unselectedmemory cellsARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-11187-96 NATURE COMMUNICATIONS |         (2019) 10:3161 | https://doi.org/10.1038/s41467-019-11187-9 | www.nature.com/naturecommunicationswww.nature.com/naturecommunicationsReceived: 22 March 2019 Accepted: 19 June 2019References1. Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies forcomputing and data storage on a single chip. Nature 547, 74 (2017).2. Wright, E. P. G. Electric connecting device. US2667542A (1954).3. Kim, T.-W. et al. All-organic photopatterned one diode-one resistor cell arrayfor advanced organic nonvolatile memory applications. Adv. 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H., Cervenka, J., Watanabe, K., Taniguchi, T. & Chen, Y. Strongoxidation resistance of atomically thin boron nitride nanosheets. ACS Nano. 8,1457–1462 (2014).AcknowledgementsThis work was supported by the Samsung Research Funding & Incubation Center ofSamsung Electronics, under project no. SRFC-MA1701-01. L. Sun acknowledges supportfrom the Korea Research Fellowship Program through the National Research Foundationof Korea (NRF) funded by the Ministry of Science and ICT under grant no. NRF-2017H1D3A1A01013759. K.W and T.T acknowledge support from the ElementalStrategy Initiative conducted by the MEXT, Japan, A3 foresight by JSPS and the CREST(JPMJCR15F3), JST. R. Zhao acknowledges support from Singapore Ministry of Edu-cation Academic Research Fund Tier 2 grant with no. MOE2016-T2-2-141.Author contributionsAll authors participated in scientific discussion. L. Sun fabricated the devices and devicearrays. Y. Zhang characterized the memory cells. Y. Zhang, R. Zhao, G. Han, and Y.-M.Kim conducted HR-TEM. L. Sun, J. Jiang and G. Hwang contribute to the fabrication offlexible devices. B. Joo, W. Yu, and B.-S. Kong simulated integrated device characteristicsby a SPICE modeling. K. Watanabe and T. Taniguchi provided h-BN. Y. Zhang sum-marized the comparison of device performances and wrote the device characterizationprocess. L. Sun, H. Yang wrote the manuscript and all author attended the revision ofmanuscript. R. Zhao and H. Yang are the principle investigators.Additional informationSupplementary Information accompanies this paper at https://doi.org/10.1038/s41467-019-11187-9.Competing interests: The authors declare no competing interests.Reprints and permission information is available online at http://npg.nature.com/reprintsandpermissions/Peer review information: Nature Communications thanks Gianluca Fiori, Zheng Liu andother anonymous reviewers for their contribution to the peer review of this work.Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims inpublished maps and institutional affiliations.Open Access This article is licensed under a Creative CommonsAttribution 4.0 International License, which permits use, sharing,adaptation, distribution and reproduction in any medium or format, as long as you giveappropriate credit to the original author(s) and the source, provide a link to the CreativeCommons license, and indicate if changes were made. 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To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.© The Author(s) 2019NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-11187-9 ARTICLENATURE COMMUNICATIONS |         (2019) 10:3161 | https://doi.org/10.1038/s41467-019-11187-9 | www.nature.com/naturecommunications 7https://doi.org/10.1038/s41467-019-11187-9https://doi.org/10.1038/s41467-019-11187-9http://npg.nature.com/reprintsandpermissions/http://npg.nature.com/reprintsandpermissions/http://creativecommons.org/licenses/by/4.0/http://creativecommons.org/licenses/by/4.0/www.nature.com/naturecommunicationswww.nature.com/naturecommunications Self-selective van der Waals heterostructures for large scale memory array Results Self-selective memory operation Microscopic origin for the selectivity Memory integration with low sneak current Demonstration of self-selective memory array with 2D �materials Discussion Methods Device fabrication procedures Device patterning details Optical characterization Key electrical measurement conditions SPICE modeling References References Acknowledgements Author contributions Competing interests ACKNOWLEDGEMENTS