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Lee et al., 2023, Silicon – van der Waals heterointegration for CMOS- compatible logic-in-memory design.pdf
Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design
Article
Creator
Mu-Pai Lee ; Caifang Gao ; Meng-Yu Tsai ; Che-Yi Lin ; Feng-Shou Yang ; Hsin-Ya Sung ; Chi Zhang ; Wenwu Li ; Jun Li ; Jianhua Zhang ; Kenji Watanabe SAMURAI ORCID ; Takashi Taniguchi SAMURAI ORCID ; Keiji Ueno ; Kazuhito Tsukagoshi SAMURAI ORCID ; Ching-Hwa Ho ; Junhao Chu ; Po-Wen Chiu ; Mengjiao Li ; Wen-Wei Wu ; Yen-Fu Lin
Keyword
van der Waals, 2D/3D heterointegration
Date published
2023-12-08
Updated at
2025-02-10 16:30:24 +0900