# Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design https://mdr.nims.go.jp/datasets/d7722aba-0cc0-4ff0-8e3f-663166ecbc3f ## File - [Lee et al., 2023, Silicon – van der Waals heterointegration for CMOS- compatible logic-in-memory design.pdf](https://mdr.nims.go.jp/filesets/1cbe6b55-a3a9-4eb9-9829-b22a4e05313b/download) ([Detail](https://mdr.nims.go.jp/filesets/1cbe6b55-a3a9-4eb9-9829-b22a4e05313b.md)) ## Id d7722aba-0cc0-4ff0-8e3f-663166ecbc3f ## Local identifier ## Visibility open_to_public ## State published ## Created at 2025-02-09T23:09:42.407389Z ## Updated at 2025-02-10T07:30:24.707135Z ## Published at 2025-02-10T07:30:24.850793Z ## Doi ## First published url https://doi.org/10.1126/sciadv.adk1597 ## Date published 2023-12-08 ## Recorded date published 2023-12-8 ## Resource type journal_article ## Manuscript type vor ## Collection ## Title - title: Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design title_type: original lang: en ## Description - description: 'The intensive data-centered computational requirement leads to the development of a computing-in-memory architecture that can blur the boundary between memory and process units. However, the implementation of silicon CMOS-based computing-in- memory faces challenges in complicated circuit design and static power dissipation, especially in a digital manner, i.e., logic-in-memory, which requires both nonvolatility and reconfigurability. Here, we report a universal design of nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By exploiting the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Two critical merits jointly enable desirable performance, including precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85 °C), and near-ideal subthreshold swing (80 mV dec1 ). A comprehensive investigation of dynamic charge fluctuations offers a holistic understanding of the nonvolatile reconfigurability origins (a trap level of 10E13 cm2 eV1 ). We further cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as a high-gain (65 at V dd = 0.5 V) logic inverter and logic gates. Our devices with simplified circuit design and manufacturing provide an innovative 3D heterointegration prototype for future computing-in-memory hardware. ' description_type: abstract lang: und ## Creator - name: Mu-Pai Lee role: author - name: Caifang Gao role: author - name: Meng-Yu Tsai role: author - name: Che-Yi Lin role: author - name: Feng-Shou Yang role: author - name: Hsin-Ya Sung role: author - name: Chi Zhang role: author - name: Wenwu Li role: author - name: Jun Li role: author - name: Jianhua Zhang role: author - name: Kenji Watanabe role: author orcid: https://orcid.org/0000-0003-3701-8119 organization: National Institute for Materials Science ror: https://ror.org/026v1ze26 - name: Takashi Taniguchi role: author orcid: https://orcid.org/0000-0002-1467-3105 organization: National Institute for Materials Science ror: https://ror.org/026v1ze26 - name: Keiji Ueno role: author - name: Kazuhito Tsukagoshi role: author orcid: https://orcid.org/0000-0001-9710-2692 organization: National Institute for Materials Science ror: https://ror.org/026v1ze26 - name: Ching-Hwa Ho role: author - name: Junhao Chu role: author - name: Po-Wen Chiu role: author - name: Mengjiao Li role: author - name: Wen-Wei Wu role: author - name: Yen-Fu Lin role: author ## Contact agent ## Publisher organization: American Association for the Advancement of Science (AAAS) ## Managing organization ## Keyword - subject: van der Waals schema: not_defined - subject: 2D/3D heterointegration schema: not_defined ## Rights - identifier: https://creativecommons.org/licenses/by/4.0/ ## Other identifier(s) ## Data origin - data_origin_type: other ## Embargo ## Journal - title: Science Advances issn: '23752548' volume: '49' issue: '9' article_number: adk1597 ## Conference ## Related item ## Funding ## Instrument ## Instrument operator ## Instrument managing organization ## Measurement method ## Specimen ## Chemical composition ## Structure for specimen ## Structural feature for specimen ## Specific property for specimen ## Process for specimen treatment ## Computational method ## Energy level/transition state ## Software ## Custom property ## Fileset - id: 1cbe6b55-a3a9-4eb9-9829-b22a4e05313b filename: Lee et al., 2023, Silicon – van der Waals heterointegration for CMOS- compatible logic-in-memory design.pdf content_type: application/pdf size: 1299474 md5: e929dd536dde792cd7e88d149b8a978a ## Thumbnail fileset_id: 1cbe6b55-a3a9-4eb9-9829-b22a4e05313b filename: Lee et al., 2023, Silicon – van der Waals heterointegration for CMOS- compatible logic-in-memory design.pdf