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Semiconductor nanowires (NWs) have recently attracted great attention as a building block candidate to overcome the physical limitations associated with device miniaturization and high degree of integration. The long-term research aim is to realize a promising device architecture called the vertical gate-all-around (GAA) NW transistors, which utilize semiconducting Ge NWs to break through the device performance. Our goal for the GAA-NW transistors is to establish a technique that enables vertical Ge NW growth with precisely controlled position and diameter by using electron beam lithography and conventional lift-off processes to define the location and size of circular Au thin film patterns. In this paper, we investigated the behavior of the Au–Ge eutectic at the initial stages of Ge growth toward the vertical growth of Ge NWs via the VLS method. When Ge gas was supplied to Au thin film patterns, we observed that the circular Au disk patterns transformed into an Au–Ge eutectic liquid and, subsequently, aggregated into a spherical form at a certain point (between 4 and 7 min) of the annealing at 360 °C. In addition, we confirmed that a higher GeH₄ partial pressure and a lower growth temperature led to the faster Ge NW growth. However, the growth at the low temperature of 330 °C tended to have a poor uniformity, implying a trade-off between the growth rate and the structural uniformity of Ge NWs.

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キーワード: Nanowires, Chemical Vapor Depsition, VLS, Selective-Area Growth, Semiconductor

会議: The 10th International Symposium on Control of Semiconductor Interface, International Conference on Silicon Epitaxy, and International SiGe Technology and Device Meeting (ISCSI-X & ICSI/ISTDM 2025) (2025-11-10 - 2025-11-13)

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原稿種別: 著者最終稿 (Accepted manuscript)

MDR DOI: https://doi.org/10.48505/nims.5908

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更新時刻: 2025-11-14 12:30:04 +0900

MDRでの公開時刻: 2025-11-14 12:23:52 +0900