# Van der Waals polarity-engineered 3D integration of 2D complementary logic

https://mdr.nims.go.jp/datasets/727a1add-801f-4264-9ea0-40ab08db3819

## File

- [s41586-024-07438-5.pdf](https://mdr.nims.go.jp/filesets/748c7f00-22f5-47d0-8042-11a0d8780083/download) ([Detail](https://mdr.nims.go.jp/filesets/748c7f00-22f5-47d0-8042-11a0d8780083.md))

## Id

727a1add-801f-4264-9ea0-40ab08db3819

## Local identifier



## Visibility

open_to_public

## State

published

## Created at

2025-08-01T06:41:34.334306Z

## Updated at

2025-08-01T23:30:31.934331Z

## Published at

2025-08-01T23:17:30.680243Z

## Doi



## First published url

https://doi.org/10.1038/s41586-024-07438-5

## Date published

2024-06-13

## Recorded date published

2024-6-13

## Resource type

journal_article

## Manuscript type

vor

## Collection



## Title

- title: Van der Waals polarity-engineered 3D integration of 2D complementary logic
  title_type: original
  lang: en

## Description

- description: Vertical three-dimensional integration of two-dimensional (2D) semiconductors
    holds great promise, as it offers the possibility to scale up logic layers in
    the z axis1,2,3. Indeed, vertical complementary field-effect transistors (CFETs)
    built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers
    with different carrier types6,7,8, have been demonstrated recently. However, so
    far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs.
    9,10,11,12,13,14,15,16,17) and MoS2 (refs. 11,18,19,20,21,22,23,24,25,26,27,28))
    in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly
    impeded the bottom-up scaling of complementary logic circuitries. Here we show
    that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der
    Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier
    polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW
    interfacial coupling. The consequential band alignment yields transistors with
    room-temperature hole mobilities up to approximately 425 cm2 V−1 s−1, on/off ratios
    reaching 106 and air-stable performance for over one year. Based on this approach,
    vertically constructed complementary logic, including inverters with 6 vdW layers,
    NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated.
    Our findings of polarity-engineered p- and n-type 2D semiconductor channels with
    and without vdW intercalation are robust and universal to various materials and
    thus may throw light on future three-dimensional vertically integrated circuits
    based on 2D logic gates.
  description_type: abstract
  lang: en

## Creator

- name: Yimeng Guo
  role: author
- name: Jiangxu Li
  role: author
- name: Xuepeng Zhan
  role: author
- name: Chunwen Wang
  role: author
- name: Min Li
  role: author
- name: Biao Zhang
  role: author
- name: Zirui Wang
  role: author
- name: Yueyang Liu
  role: author
- name: Kaining Yang
  role: author
- name: Hai Wang
  role: author
- name: Wanying Li
  role: author
- name: Pingfan Gu
  role: author
- name: Zhaoping Luo
  role: author
- name: Yingjia Liu
  role: author
- name: Peitao Liu
  role: author
- name: Bo Chen
  role: author
- name: Kenji Watanabe
  role: author
  orcid: https://orcid.org/0000-0003-3701-8119
  organization: National Institute for Materials Science
- name: Takashi Taniguchi
  role: author
  orcid: https://orcid.org/0000-0002-1467-3105
  organization: National Institute for Materials Science
- name: Xing-Qiu Chen
  role: author
- name: Chengbing Qin
  role: author
- name: Jiezhi Chen
  role: author
- name: Dongming Sun
  role: author
- name: Jing Zhang
  role: author
- name: Runsheng Wang
  role: author
- name: Jianpeng Liu
  role: author
- name: Yu Ye
  role: author
- name: Xiuyan Li
  role: author
- name: Yanglong Hou
  role: author
- name: Wu Zhou
  role: author
- name: Hanwen Wang
  role: author
- name: Zheng Han
  role: author

## Contact agent



## Publisher

organization: Springer Science and Business Media LLC

## Managing organization



## Keyword

- subject: Polarity Engineering of 2D Semiconductors
  schema: not_defined
- subject: Vertically Integrated Logic Circuits
  schema: not_defined
- subject: van der Waals Interfacial Coupling
  schema: not_defined

## Rights

- identifier: https://creativecommons.org/licenses/by/4.0/

## Other identifier(s)



## Data origin

- data_origin_type: other

## Embargo



## Journal

- title: Nature
  issn: '00280836'
  volume: '630'
  issue: '8016'
  start_page: 346
  end_page: 352

## Conference



## Related item



## Funding



## Instrument



## Instrument operator



## Instrument managing organization



## Measurement method



## Specimen



## Chemical composition



## Structure for specimen



## Structural feature for specimen



## Specific property for specimen



## Process for specimen treatment



## Computational method



## Energy level/transition state



## Software



## Custom property



## Fileset

- id: 748c7f00-22f5-47d0-8042-11a0d8780083
  filename: s41586-024-07438-5.pdf
  content_type: application/pdf
  size: 16462841
  md5: bcd00d5e16ca6540d374557913c86ef8

## Thumbnail

fileset_id: 748c7f00-22f5-47d0-8042-11a0d8780083
filename: s41586-024-07438-5.pdf