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説明:

We demonstrate an ultralow-voltage ternary multivalued logic (MVL) inverter based on an extended p-channel antiambipolar transistor (Ep-AAT) employing an optimized HfO2/polystyrene gate dielectric stack. The HfO2 dielectric enables low-voltage operation, while the polystyrene surface layer provides a low-surface-energy interface for stable organic channel formation. The Ep-AAT exhibits an intrinsic N-shaped transfer characteristic with a clear negative transconductance region, explained by the combined contributions of the N1, P1, and P2 channels. Integrated with an n-type transistor, the Ep-AAT realizes a ternary MVL inverter with three distinct logic states at a supply voltage of 2 V without additional circuit complexity. These results highlight the potential of HfO2/polystyrene-based Ep-AATs for MVL circuits.

権利情報:

• Creative Commons BY Attribution 4.0 International
  

キーワード: Anti-ambipolar transistor, Negative transconductance, Ternary multi-valued logic, Ultralowvoltage inverter, High-k gate dielectric

刊行年月日: 2026-10-06

出版者: Institute of Electrical and Electronics Engineers (IEEE)

掲載誌:

• IEEE Journal of the Electron Devices Society (ISSN: 21686734) vol. 14 p. 875-880

研究助成金:

• National Research Foundation of Korea
• Korean Government [Ministry of Science and ICT (MSIT)] RS-2024-00438999
• Korea Basic Science Institute
• Korean Government RS-2025-00558813
• Japan Society for the Promotion of Science (JSPS) KAKENHI 23H00269
• Canon Foundation
• Electronics and Telecommunications Research Institute
• Korean Government, Neuromorphic Computing, Synaptic Device, Neuron Device, Activation function, Vertical Stacking 4011-2026-00002
• Korea Industrial Technology Association KOITA-2026-017
• Innovative Science and Technology Initiative for Security, Acquisition, Technology and Logistics Agency JPJ004596

原稿種別: 出版者版 (Version of record)

MDR DOI:

公開URL: https://doi.org/10.1109/jeds.2026.3737142

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更新時刻: 2026-11-04 18:41:23 +0900

MDRでの公開時刻: 2026-11-05 10:27:33 +0900